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data sheet, rev. 1.31, nov. 2005 communications samurai-6m/mx 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996mx - green package version) adm6996m/mx, version ac
edition 2005-11-25 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: template_a4_3.0.fm / 3 / 2005-01-17 trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. adm6996m/mx, 6 port 10/100 mbit/s single chip ethernet switch controller (adm6996mx - green package version) revision history: 2005-11-25, rev. 1.31 previous version: rev. 1.23 page/date subjects (major changes since last revision) page 15 rev. 1.2: modify analog pins number (rxp4-0, rxn4-0, txp4-0 and txn4-0) page 81-82 rev. 1.21: rearrange 0e h and 0f h registers map page 22 rev. 1.22: modify lnkfp5 pin description/1 b , link failed 2005-07-04 changed to the new infineon format 2005-07-04 rev. 1.22 changed to rev. 1.23 2005-08-23 rev 1.3: update in content 2005-11-01 revision 1.3 changed to revision 1.31 minor change. included green package information
data sheet 4 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 samurai-6m/6mx (adm6996m/mx) overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 data lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pin description by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.2 buffers and queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.3 full duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.4 half duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.5 back-off algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.6 inter-packet gap (ipg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.7 trunking function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.8 illegal frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.9 broadcast storm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.10 bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.11 smart discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.12 led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.12.1 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.12.2 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.12.3 circuit for single led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.12.4 circuit for dual led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.13 packet identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.13.1 span packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.13.2 management packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.13.3 cross_vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.14 tagged vlan or port vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1.14.1 vlan filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1.14.2 port vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1.14.3 tagged vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.1.14.4 vid for comparison and carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . 38 3.1.14.5 admit only vlan-tagged packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.14.6 vid check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.14.7 fid and vlan boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.14.8 ingress filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.14.9 vlan violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.14.10 txtag carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.14.11 tagged member carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . . . . . . . . 40 table of contents
data sheet 5 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx table of contents 3.1.14.12 egress tag rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.14.13 tagged pri carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.14.14 cfi carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.14.15 egress tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.15 priority queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.15.1 system pri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.15.2 queue assigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.15.3 configure samurai qos function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.16 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.16.1 dynamic learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.16.2 manual learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.16.3 learning table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.16.3.1 entry format in the learning table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.16.3.2 the registers accessing the learning table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1.16.3.3 rules to access the learning table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.16.3.4 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.17 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.18 hardware based igmp snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.18.1 entry format of igmp membership table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1.18.2 the registers accessing the igmp membership table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1.18.3 igmp snooping introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.19 source violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.1.20 packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.20.1 control table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.20.2 default output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.20.3 forwarding algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.21 802.1x security function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.22 special tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.1.22.1 special tag for the receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.1.22.2 special tag for the transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 port4 and port5 mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.1 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.2 speed/duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.4 hardware, eeprom and smi interface for configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.4.1 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.4.2 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.4.3 smi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5 the hardware difference between adm6996m/mx and adm6996f . . . . . . . . . . . . . . . . . . . . . . . . 80 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.1 eeprom basic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2 eeprom extended registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.3 counter and switch status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.4 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.1 tx/fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.1.1 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.1.2 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.2 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.3 ac characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
samurai-6m/mx adm6996m/mx table of contents data sheet 6 rev. 1.31, 2005-11-25 5.3.1 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 5.3.2 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.3.3 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 5.3.4 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.3.5 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.3.6 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 5.3.7 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.3.8 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.3.9 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.3.10 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.3.11 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.3.12 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.3.13 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.3.14 mdc/mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05 6.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
data sheet 7 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx list of figures figure 1 samurai-6m/6mx (adm6996m/mx) block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2 4 tp/fx port + 2 mii port 128 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 3 circuit for single color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4 circuit for dual color led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5 to configure samurai qos function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6 flow chart of 802.1x security function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 7 adm6996m/mx to cpu with single mii connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 8 the configurations of the implementation by adm6996m/mx special tag functions . . . . . . . . . . 66 figure 9 software operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 10 adm6996m/mx to cpu with dual mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 11 100m full duplex mac to mac mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 12 pcs to mac mii connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 13 interconnection between samurai-6m/6mx (adm6996m/mx), eeprom and cpu . . . . . . . . . . . 73 figure 14 the power-on-sequence of samurai. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 15 timing diagram of rc, eecs and eesk (with correct signature eeprom). . . . . . . . . . . . . . . . . 77 figure 16 timing diagram of rc, eecs and eesk (without eeprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 17 smi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 18 tp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 19 fx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 20 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 21 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 22 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 23 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 24 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 25 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 26 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 27 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 28 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 29 reduce mii timing (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 30 reduce mii timing (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 31 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 32 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 33 sdc/sdio timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 34 mdc/mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 35 p-pqfp-128 outside dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 list of figures
data sheet 8 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx list of tables table 1 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3 io signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 smart disacrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5 discard ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6 single color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7 dual color led display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8 packet identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9 packet identification groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10 span packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11 management packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12 cross_vlan packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13 vlan filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 14 vid comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15 fid search algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16 vlan boundary search algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17 txtag carried through samurai-6m/6mx (adm6996m/mx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18 egress tag result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19 tagged pri carried . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20 cfi carried . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21 priority queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 22 queue assigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23 control register description for accessing the address table . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24 description for command and access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25 status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26 description for the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27 control register description for accessing the igmp membership table . . . . . . . . . . . . . . . . . . 52 table 28 description for command and access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29 entry format of igmp membership table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30 ipv4/igmp/general query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31 ipv4/igmp/v1 report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32 ipv4/igmp/general query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33 ipv4/igmp/v1 report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34 ipv4/igmp/v2 report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 35 ipv4/igmp/v2 leave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 36 ipv4/igmp/group-specific query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 37 igmp membership table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 38 forwarding algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 39 special tag for the receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 40 option for special tag transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 41 special tag for the transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 42 special tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 43 set wan/lan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 44 packets identified by adm6996m/mx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 45 speed/duplex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 46 hardware setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 47 (d) the pin type of eecs, eesk, edi and edo during the operation . . . . . . . . . . . . . . . . . . . . 79 table 48 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 49 pin description(qfp128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 list of tables
data sheet 9 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx list of tables table 50 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 51 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 52 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 53 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54 p1~p5 basic control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 55 px_ec registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 56 pxso registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 57 vfxl registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 58 vfxh registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 59 tfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 60 pfx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 61 rax registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 62 tufx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 63 clx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 64 chx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 65 phy_cx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 66 phy_sx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 67 phy_ix_a registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 68 phy_ix_b registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 69 anapx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 70 anlpax registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 71 anex registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 72 nptx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 73 lpnpx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 74 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 75 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 76 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 77 dc electrical characteristics for 3.3 v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 78 xtal/osc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 91 under v cc3o = 2.97v ~ 3.63 v, t j = 0 c ~ 115 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 79 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 80 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 81 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 82 10-base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 83 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 84 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 85 rmii refclk input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 86 rmii refclk output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 87 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 88 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 89 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 90 sdc/sdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 91 mdc/mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
samurai-6m/mx adm6996m/mx product overview data sheet 10 rev. 1.31, 2005-11-25 1 product overview 1.1 samurai-6m/6mx (adm6996m/mx) overview the samurai-6m/6mx (adm6996m/mx) is a high performance, low cost, highly integrated (controller, phy and memory) 6-port mii mac ports with five supporting 10/100 mbit/s phy tx/fx ethernet full/half duplex operation. the samurai-6m/6mx (adm6996m/mx) is intended for applications such as stand alone bridges for the low cost soho markets such as 5-port switches and router applications. the samurai-6mx (adm6996mx) is the environmentally friendly ?green? package version. the samurai-6m/6mx (adm6996m/mx) provides functions such as: 802.1p(q.o.s.), 802.1q(vlan), port mac address locking, management, port status, tp auto-mdix, 25m crystal & extra mii port functions to meet customer requests on switch demand. the samurai-6m/6mx (adm6996m/mx) also supports back pressure in half-duplex mode and the 802.3x flow control pause packet in full-duplex mode to prevent packet loss when buffers are full. when back pressure is enabled, and there is no receive buffer available for the incoming packet, the samurai-6m/6mx (adm6996m/mx) will issue a jam pattern on the receiving port in half duplex mode and issue the 802.3x pause packet back to the receiving end in full duplex mode. the built-in sram used for the packet buffer is divided into 256 bytes per block to achieve the optimized memory utilization through complicated link lists on packets with various lengths. the samurai-6m/6mx (adm6996m/mx) also supports priority features using port-based, vlan and ip tos field checking. users can easily set different priority modes in individual ports, through a small low-cost micro controller when initializing or configuring on-the-fly. each output port supports four queues in the way of fixed n: 1 fairness queuing to fit the bandwidth demand on various types of packets such as voice, video and data. 802.1q, tag/untag, and up to 16 groups of vlan are also supported. an intelligent address recognition algorithm allows samurai-6m/6mx (adm6996m/mx) to recognize up to 2k different mac addresses and enables filtering and forwarding at full wire speed. port mac address locking function is also supported by samurai-6m/6mx (adm6996m/mx) to use on building internet access to prevent multiple users sharing one port. 1.2 features ? five 10m/100m auto-detect half/full duplex switch ports with tx/fx interfaces and one mii/gpsi/rmii port ? 2k mac address tables with 4-ways associative hash algorithm ? four queues for qos ? priority features by port-based, 802.1p, ip tos, diffserv, tcp/udp destination port application-based of packets ? store & forward architecture and performs forwarding and filtering at non-blocking full wire speed ? per port single/dual color mode with power on auto diagnostic. collision/duplex led can be separated using register setting ? 802.3x flow control pause packet for full duplex ? back pressure function for half duplex operation ? supports packet lengths up to 1518/1522 (default)/1536/1784 bytes in maximum ? scalable per port bandwidth control (both ingress and egress). (step = 64k, up to 100m) ? broadcast/multicast storm suppression ? 802.1q vlan. up to 16 vlan groups are implemented by full 12 bits vid matching ? mac clone function to enable multiple wan application ? tp interface auto mdix function for auto tx/rx swap by strapping-pin.
data sheet 11 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx product overview ? interrupt pin, interrupt register and interrupt mask register. programmable interrupt polarity (default active low) ? easy management 32-bit smart counter for per port rx/tx byte/packet count, 16-bit smart counter for per port error count and collision count ? supports 32 hardware igmp table (multicast table) ? mac address table is accessible ? supports 802.1x security function ? supports spanning tree protocol ? supports internal counter/phy status output for management system ? 25m crystal ? 128 qfp package with 0.18 m technology. 1.8 v/3.3 v power supply. ? 1.0 w low power consumption. 1.3 applications samurai-6m/6mx (adm6996m/mx): ? soho 5-port switch ? 5-port switch + router with 2 mii cpu interface
samurai-6m/mx adm6996m/mx product overview data sheet 12 rev. 1.31, 2005-11-25 1.4 block diagram figure 1 samurai-6m/6mx (adm6996m/mx) block diagram 1.5 data lengths qword: 64 bits dword: 32 bits word: 16 bits byte: 8 bits nibble: 4 bits po rt 0 po rt 1 po rt 2 po rt 3 mlt3 nrz nrzi digital equalizer nrz to 5b 5b to nrz txn7 txp7 driver a/d con v ert er rx n 7 rx p7 base line correction clock generator bias 10/100m mac descrambler data handler jabber detector carrier integrity monitor fifo pa rtitio n handl er scramble r transmit state machine led display control twisted pai r interface led interface ... 10/100m mac 10/100m mac 10/100m mac switching fabric embedded memory mii interface memory bist eeprom handler eeprom interface mii2rmii mii2gpsi mii2hdlc m i i /rm i i /gpsi /hdl c interface
data sheet 13 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 2 interface description this chapter describes the interface descriptions for the samurai-6m/6mx (adm6996m/mx) ?pin diagram ? abbreviations ? pin description by function 2.1 pin diagram figure 2 shows the pin diagram for the samurai-6m/6mx (adm6996m/mx). figure 2 4 tp/fx port + 2 mii port 128 pin diagram p4txd3 p4txd2 p4txd1 (p4_busmd1) p4txd0 (p4_busmd0) dupcol4/dphalfp4 gndo vcc3o dupcol3 dupcol2 (bpen) dupcol1(phyas1) dupcol0(recanen) p4txen p4txclk vccik p4rxclk gndik rc xi xo vccpll gndpll control vref gndbias rtx vccbias gndik (gfcen) p5txd0 p4fx (p5_busmd0)p5txd1 (p5_busmd1)p5txd2 (sdio_md)p5txd3 p5col p5crs p5rxd3 p5rxd2 p5rxd1 p5rxd0 p5rxdv spdtnp4/ldspd4 gndo vcc3o ldspd3 ldspd2 vccik gndik mdc ldspd1 ldspd0 test mdio p4rxer in t_n p5txen(phyas0) p5txclk/refclk_out p5 rx er wait_init gndo vc c3 o p5 rx cl k/r efc lk_in p4 rx dv p4 rx d0 vc c2 ik gndik p4 cr s p4 col edi (dual color) eecs eesk (xoven) vc c2 ik gndik edo cko25m cf g0 gndo vc c3 o spdtnp5 lnkfp5 dp hal fp 5 lnkact4/lnkfp4 gndik vc c2 ik lnkact3 lnkact2 lnkact1 lnkact0 gndo p4 rx d1 p4 rx d2 p4 rx d3 samurai-m adm6996m vcca2 txp4 txn4 gnda gnda rx p4 rx n4 vccad rx n3 rx p3 gnda gnda txn3 txp3 vcca2 vccad rx n2 rx p2 gnda txn2 txp2 vcca2 vccad rx n1 rx p1 gnda gnda txn1 txp1 vcca2 vccad rx n0 rx p0 gnda gnda txn0 txp0 vcca2 104 103 105 112 111 110 109 108 107 106 113 114 116 115 117 124 123 122 121 120 119 118 125 126 128 127 68 69 70 71 72 73 74 75 76 77 67 66 65 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 10 1 10 2 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 40 41 39 63 64 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 1 31 32 33 34 35 36 37 38
samurai-6m/mx adm6996m/mx interface description data sheet 14 rev. 1.31, 2005-11-25 2.2 abbreviations standard abbreviations for i/o tables: 2.3 pin description by function samurai-6m/6mx (adm6996m/mx) pins are categorized into one of the following groups: ? network media connection ? port 4 mii interface ? port 5 mii interface ? led interface ? eeprom interface ? power/ground, 48 pins ? miscellaneous table 1 abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 2 abbreviations for buffer type abbreviations description z high impedance pu pull up, 10 k ? pd pull down, 10 k ? ts tristate capability: the corresponding pin has 3 operational states: low, high and high- impedance. od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics
data sheet 15 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description note: table 1 can be used for reference. table 3 io signals pin or ball no. name pin type buffer type function network media connection 33 rxp_4 ai/o ana receive pair differential data is received on this pin. 29 rxp_3 21 rxp_2 14 rxp_1 6rxp_0 32 rxn_4 ai/o ana 30 rxn_3 22 rxn_2 15 rxn_1 7rxn_0 37 txp_4 ai/o ana transmit pair differential data is transmitted on this pin. 25 txp_3 18 txp_2 10 txp_1 2txp_0 36 txn_4 ai/o ana 26 txn_3 19 txn_2 11 txn_1 3txn_0 port 4 mii interface 74 mmii_p4rxd0 i pd, lvttl port 4 receive data bit 0 in mac mii mode in mac mii mode, the bit is the lsb of mii receive data, synchronous to the rising edge of mmii_p4rxclk. pmii_p4rxd0 o 8 ma, pd, lvttl port 4 receive data bit 0 in pcs mii mode when port 4 is operating in pcs mii mode, the bit is the lsb of mii receive data output and synchronous to the rising edge of pmii_p4rxclk. 102 mmii_p4rxd3 i pd, lvttl port 4 receive data bit 3 in mac mii mode in mac mii mode, this bit is bit[3] of mii receive data, and synchronous to the rising edge of mmii_p4rxclk. pmii_p4rxd3 o 8 ma, pd, lvttl port 4 receive data bit 3 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[3] of mii receive data output and synchronous to the rising edge of pmii_p4rxclk.
samurai-6m/mx adm6996m/mx interface description data sheet 16 rev. 1.31, 2005-11-25 101 mmii_p4rxd2 i pd, lvttl port 4 receive data bit 2 in mac mii mode in mac mii mode, this pin is bit[2] of mii receive data, and synchronous to the rising edge of mmii_p4rxclk. pmii_p4rxd2 o 8 ma, pd, lvttl port 4 receive data bit 2 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[2] of mii receive data output and synchronous to the rising edge of pmii_p4rxclk. 100 mmii_p4rxd1 i pd, lvttl port 4 receive data bit 1 in mac mii mode in mac mii mode, this pin is bit[1] of mii receive data, and synchronous to the rising edge of mmii_p4rxclk. pmii_p4rxd1 o 8 ma, pd, lvttl port 4 receive data bit 1 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[1] of mii receive data output and synchronous to the rising edge of pmii_p4rxclk. 73 mmii_p4rxdv i pd, lvttl port 4 receive data valid in mac mii mode active high to indicate that the data on mmii_p4rxd[3:0] is valid. synchronous to the rising edge of mmii_p4rxclk. pmii_p4rxdv o 8 ma, pd, lvttl port 4 receive data valid in pcs mii mode when port 4 is operating in pcs mii mode, this pin is an active high output signal to indicate pmii_p4rxd[3:0] is valid. synchronous to the rising edge of pmii_p4rxclk. 39 mii_p4rxer i pd, lvttl port 4 receive error in mac mii mode active high to indicate that there is symbol error on the mii_p4rxd[3:0]. only valid in 100m operation. 77 mmii_p4crs i pd, lvttl port 4 carrier sense in mac mii mode in full duplex mode, mmii_p4crs reflects the receive carrier sense situation on medium only; in half duplex, crs will be high both in receive and transmit condition. pmii_p4crs o 8 ma, pd, lvttl port 4 carrier sense in pcs mii mode when port 4 is operating in pcs mii mode, this pin is used to output carrier sense status. 78 mmii_p4col i pd, lvttl port 4 collision input in mac mii mode active high to indicate that there is collision on the medium. stay low in full duplex operation. pmii_p4col o 8 ma, pd, lvttl port 4 collision output in pcs mii mode when port 4 is operating in pcs mii mode, this pin is used to output collision status. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 17 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 106 p4_busmd0 i pd, lvttl port 4 bus type configuration 0 value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) for port 4 configuration bit 0. combined with cfg0 and p4_busmd1 , samurai-6m/6mx (adm6996m/mx) provides 4 bus type for port 4. see cfg0 pin description for more details. note: power on setting mmii_p4txd0 o 8 ma, pd, lvttl port 4 transmit data bit 0 in mac mii mode the lsb bit of mac mii transmit data of port 4. synchronous to the rising edge of mmii_p4txclk. pmii_p4txd0 i pd, lvttl port 4 transmit data bit 0 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is the lsb of mii transmit data input and synchronous to the rising edge of pmii_p4txclk. 105 p4_busmd1 i pd, lvttl port 4 bus type configuration 1 value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) for port 4 configuration bit 1. combined with cfg0 and p4_busmd0 , samurai-6m/6mx (adm6996m/mx) provides 4 bus type for port 4. see cfg0 for more details. note: power on setting mmii_p4txd1 o 8 ma, pd, lvttl port 4 transmit data bit 1 in mac mii mode the bit[1] of mac mii transmit data of port 4. synchronous to the rising edge of mmii_p4txclk. pmii_p4txd1 i pd, lvttl port 4 transmit data bit 1 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[1] of mii transmit data input and synchronous to the rising edge of pmii_p4txclk. 103 mmii_p4txd3 o 8 ma, pd, lvttl port 4 transmit data bit 3 in mac mii mode the bit[3] of mac mii transmit data of port 4. synchronous to the rising edge of mmii_p4txclk. pmii_p4txd3 i pd, lvttl port 4 transmit data bit 3 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[3] of mii transmit data input and synchronous to the rising edge of pmii_p4txclk. 104 mmii_p4txd2 o 8 ma, pd, lvttl port 4 transmit data bit 2 in mac mii mode the bit[2] of mac mii transmit data of port 4. synchronous to the rising edge of mmii_p4txclk. pmii_p4txd2 i pd, lvttl port 4 transmit data bit 2 in pcs mii mode when port 4 is operating in pcs mii mode, this pin is bit[2] of mii transmit data input and synchronous to the rising edge of pmii_p4txclk. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 18 rev. 1.31, 2005-11-25 114 mmii_p4txen o 8 ma, pd, lvttl port 4 transmit enable in mac mii mode output by samurai-6m/6mx (adm6996m/mx) at the rising edge of mmii_p4txclk when samurai-6m/6mx (adm6996m/mx) is programmed to mac type mii. pmii_p4txen i pd, lvttl port 4 transmit enab le in pcs mii mode it is the mii transmit enable input to samurai-6m/6mx (adm6996m/mx) when programmed to pcs type mii. 117 mmii_p4rxclk i pd, lvttl port 4 receive clock in mac mii mode 25mhz free running clock in 100m mode and 2.5 mhz free running clock in 10m mode. mmii_p4rxdv and mmii_p4rxd[3:0] should be synchronous to the rising edge of this clock pmii_p4rxclk o 8 ma, pd, lvttl port 4 receive clock in pcs mii mode 25mhz free running clock in 100m mode and 2.5 mhz free running clock in 10m mode. pmii_p4rxdv and pmii_p4rxd[3:0] should be synchronous to the rising edge of this clock 115 mmii_p4txclk i pd, lvttl port 4 transmit clock in mac mii mode 25mhz free running clock in 100m mode and 2.5 mhz free running clock in 10m mode. mmii_p4txen and mmii_p4txd[3:0] should be synchronous to the rising edge of this clock pmii_p4txclk o 8 ma, pd, lvttl port 4 transmit clock in pcs mii mode 25mhz free running clock in 100m mode and 2.5 mhz free running clock in 10m mode. pmii_p4txen and pmii_p4txd[3:0] should be synchronous to the rising edge of this clock 62 p4fx i pd, lvttl port 4 fiber selection for pcs mii/phy mode during power on reset, value will be latched by samurai- 6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as port 4 fiber select. 0 b , twisted pair mode 1 b , fiber mode table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 19 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description port 5 mii interface 63 gfcen i pu, lvttl global flow control enable value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as flow control enable. note: power on setting 0 b , flow control capability is depended upon the register setting in corresponding port?s basic control register 1 b , all ports flow control capability is enabled mii_p5txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in mii mode the lsb bit of mii transmit data of port 5. synchronous to the rising edge of mii_p5txclk. gpsi_p5txd o 4 ma, pu, lvttl port 5 transmit data in gpsi mode when port 5 is operating in gpsi mode, this pin acts as gpsi transmit data. synchronous to the rising edge of gpsi_p5txclk. rmii_p5txd0 o 4 ma, pu, lvttl port 5 transmit data bit 0 in rmii mode when port 5 is operating in rmii mode, this pin acts as rmii transmit data bit[0]. synchronous to the rising edge of refclk_in. 61 p5_busmd0 i pd, lvttl port 5 bus mode selection bit 0 value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as port 5 bus mode selection bit 0. combined with p5_busmd1 , samurai-6m/6mx (adm6996m/mx) provides 3 bus types for port 5. p5_busmd[1:0], interface note: power on setting 00 b , mii 01 b , gpsi 10 b , rmii 11 b , reserved and not allowed mii_p5txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in mii mode the bit[1] of mii transmit data of port 5. synchronous to the rising edge of mii_p5txclk. rmii_p5txd1 o 4 ma, pd, lvttl port 5 transmit data bit 1 in rmii mode the bit[1] of rmii transmit data of port 5. synchronous to the rising edge of refclk_in. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 20 rev. 1.31, 2005-11-25 60 p5_busmd1 i pd, lvttl port 5 bus mode selection bit 1 value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as port 5 bus mode selection bit 1. see p5_busmd0 for more details. note: power on setting mii_p5txd2 o 4 ma, pd, lvttl port 5 transmit data bit 2 in mii mode the bit[2] of mii transmit data of port 5. synchronous to the rising edge of mii_p5txclk. 59 sdio_md i pd, lvttl sdc/sdio mode selection value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as sdc / sdio control signal which is used to select 16 bit mode. note: power on setting 0 b , 16 bits mode, mdc/mdio timing compatible mii_p5txd3 o 4 ma, pd, lvttl port 5 transmit data bit 3 in mii mode the msb bit of mii transmit data of port 5. synchronous to the rising edge of mii_p5txclk. 66 phyas0 i pd, lvttl phy address msb bit 0 during power on reset, value will be latched by samurai- 6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as phy start address select. phyas[1:0] = 00 b and phy address starts from 01000 b . note: power on setting mii_p5txen o 8 ma, pd, lvttl port 5 transmit enable txen in mii mode active high to indicate that the data on mii_p5txd[3:0] is valid. synchronous to the rising edge of mii_p5txclk. gpsi_p5txen o 8 ma, pd, lvttl port 5 transmit enable txen in gpsi mode active high to indicate that the data on gpsi_p5txd is valid. synchronous to the rising edge of gpsi_p5txclk. rmii_p5txen o 8 ma, pd, lvttl port 5 transmit enable txen in rmii mode active high to indicate that the data on rmii_p5txd[1:0] is valid. synchronous to the rising edge of refclk_in. 53 mii_p5rxd0 i pd, lvttl port 5 receive data bit 0 in mii mode in mii mode, the bit is the lsb of mii receive data, synchronous to the rising edge of mii_p5rxclk. gpsi_p5rxd i pd, lvttl port 5 receive data in gpsi mode in gpsi mode, this acts as receive data input, synchronous to the rising edge of gpsi_p5rxclk. rmii_p5rxd0 i pd, lvttl port 5 receive data bit 0 in rmii mode in rmii mode, the bit is the lsb of rmii receive data, synchronous to the rising edge of refclk_in. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 21 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 54 mii_p5rxd1 i pd, lvttl port 5 receive data bit 1 in mii mode in mii mode, the bit is the bit[1] of mii receive data, synchronous to the rising edge of mii_p5rxclk. rmii_p5rxd1 i pd, lvttl port 5 receive data bit 1 in rmii mode in rmii mode, the bit is the msb of rmii receive data, synchronous to the rising edge of refclk_in. 55 mii_p5rxd2 i pd, lvttl port 5 receive data bit 2 in mii mode in mii mode, the bit is the bit[2] of mii receive data. synchronous to the rising edge of mii_p5rxclk. 56 mii_p5rxd3 i pd, lvttl port 5 receive data bit 3 in mii mode in mii mode, the bit is the bit[3] of mii receive data. synchronous to the rising edge of mii_p5rxclk. 52 mii_p5rxdv i pd, lvttl port 5 receive data valid in mii mode active high to indicate that the data on mii_p5rxd[3:0] is valid. synchronous to the rising edge of mii_p5rxclk. rmii_p5 crsdv ipd, lvttl port 5 carrier sense and receive data valid in rmii mode active high to indicate that the data on rmii_p5rxd[1:0] is valid. synchronous to the rising edge of refclk _in. 68 mii_p5rxer i pd, lvttl port 5 receive error in mii mode active high to indicate that there is symbol error on the mii_p5rxd[3:0]. only valid in 100m operation. rmii_p5rxer i pd, lvttl port 5 receive error in rmii mode active high to indicate that there is symbol error on the rmii_p5 rxd[1:0]. only valid in 100m operation. 57 mii_p5crs i pd, lvttl port 5 carrier sense in mii mode in full duplex mode, mii_p5crs reflects the receive carrier sense situation on medium only; in half duplex, mii_p5crs will be high both in receive and transmit condition. gpsi_p5crs i pd, lvttl port 5 carrier sense in gpsi mode in full duplex mode, gpsi_p5crs reflects the receive carrier sense situation on medium only; in half duplex, gpsi_p5crs will be high both in receive and transmit condition. 58 mii_p5col i pd, lvttl port 5 collision input in mii mode active high to indicate that there is collision on the medium. stay low in full duplex operation. gpsi_p5col i pd, lvttl port 5 collision input in gpsi mode active high to indicate that there is collision on the medium. stay low in full duplex operation. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 22 rev. 1.31, 2005-11-25 72 mii_p5rxclk i pd, lvttl port 5 receive clock input in mii mode mii_p5rxdv and mii_p5rxd[3:0] are synchronous to the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_p5 rxclk ipd, lvttl port 5 receive clock input in gpsi mode gpsi_p5rxd are synchronous to the rising edge of this clock. it is non-continuous 10 mhz clock input. refclk_in i pd, lvttl 50mhz reference clock input in rmii mode rmii_p5rxd[1:0], rmii_p5txd[1:0], rmii_p5txen and rmii_p5crsdv are synchronous to the rising edge of this clock. 67 mii_p5txclk i pd, lvttl port 5 transmit clock input in mii mode mii_p5txen and mii_p5txd[3:0] are output at the rising edge of this clock. it is free running 25 mhz clock in 100m mode and 2.5 mhz clock in 10m mode. gpsi_p5 txclk ipd, lvttl port 5 transmit clock input in gpsi mode gpsi_p5txen and gpsi_p5txd are synchronous to the rising edge of this clock. it is continuous 10 mhz clock input. refclk _ out o 8 ma, pd, lvttl 50mhz reference clock output in rmii mode this pin is used as 50 mhz reference clock signal output pin when port 5 operates in rmii mode. 89 spdtnp5 i pd, lvttl port 5 speed input 0 b , 100m 1 b , 10m 90 lnkfp5 i pd, lvttl port 5 link fail status input 0 b , link up 1 b , link failed 91 dphalfp5 i pd, lvttl port 5 duplex status input 0 b , full duplex 1 b , half duplex led interface 107 dphalfp4 i pd, lvttl port 4 duplex status input when port 4 operates under mac mii mode (see cfg0 for more details), this pins is used to select the duplex mode of port 4. 0 b , full duplex 1 b , half duplex dupcol4 o 8 ma, pd, lvttl port 4 duplex /collision led when port 4 operates under phy or pcs mii mode (see cfg0 for more details), in full duplex mode, this pin acts as duplex led for port 4; in half duplex mode, it is collision led for each port. see chapter 3.1.12 led display for more details. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 23 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 110 dupcol3 o 8 ma, pd, lvttl port 3 duplex /collision led in full duplex mode, this pin acts as duplex led for port 3; in half duplex mode, it is collision led for each port. see chapter 3.1.12 led display for more details. 111 bpen i pu, lvttl recommend back-pressure in half-duplex value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) during power on reset as the back- pressure enable in half-duplex mode. note: power on setting 0 b , disable back-pressure 1 b , enable back-pressure dupcol2 o 8 ma, pu, lvttl port 2 duplex-collision led in full duplex mode, this pin acts as port 2 duplex led; in half duplex mode, it is collision led for port 2. see chapter 3.1.12 led display for more details. 112 phyas1 i pd, lvttl recommend phy address bit 1 value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) during power on reset as the phy address recommends value bit 1. see phyas0 description for more details. note: power on setting dupcol1 o 8 ma, pd, lvttl port 1 duplex-collision led in full duplex mode, this pin acts as port 1 duplex led; in half duplex mode, it is collision led for port 1. see chapter 3.1.12 led display for more details. 113 recanen i pu, lvttl recommend auto negotiation enable only valid for twisted pair interface. programmed this bit to 1 has no effect to fiber port. note: power on setting. 0 b , disable all tp port auto negotiation capability 1 b , enable all tp port auto negotiation capability dupcol0 o 8 ma, pu, lvttl port 0 duplex-collision led in full duplex mode, this pin acts as port 0 duplex led; in half duplex mode, it is collision led for port 0. see chapter 3.1.12 led display for more details. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 24 rev. 1.31, 2005-11-25 92 lnkfp4 i pd, lvttl port 4 link fail status input when port 4 operates under mac mii mode (see cfg0 for more details), this pin is used as link control of port 4. 0 b , link up 1 b , link failed lnkact_4 o 8 ma, pd, lvttl link/activity led of port 4 when port 4 operates under phy or pcs mii mode (see cfg0 for more details), this pin is used to indicate the link/activity status of port 4, see chapter 3.1.12 led display for more details. 95 lnkact_3 o 8 ma, pd, lvttl link/activity led of port 3 to 0 used to indicate corresponding port' s link/activity status, see chapter 3.1.12 led display for more details. 96 lnkact_2 97 lnkact_1 98 lnkact_0 51 spdtnp4 i pd, lvttl port 4 speed input when port 4 operates under mac mii mode (see cfg0 for more details), this pin is used to select the operating speed of port 4. 0 b , 100m 1 b , 10m ldspd_4 o 8 ma, pd, lvttl port 4 speed led when port 4 operates under phy or pcs mii mode (see cfg0 for more details), this pin is used to indicate the speed status of port 4, see chapter 3.1.12 led display for more details. 48 ldspd_3 o 8 ma, pd, lvttl port 3 to port 0 speed led used to indicate corresponding port? s speed status, see chapter 3.1.12 led display for more details. 47 ldspd_2 43 ldspd_1 42 ldspd_0 eeprom interface 84 edo i pu, lvttl eeprom data output this pin is used to input eeprom data when reading eeprom. during samurai-6m/6mx (adm6996m/mx) initialisation, samurai-6m/6mx (adm6996m/mx) will drive eeprom interface signal to read settings from eeprom. any other devices attached to eeprom interface should drive hi-z or keep tristate during this period. see chapter 3.4.2 eeprom interface for more details. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 25 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 80 ifsel i pd, lvttl interface selection after samurai-6m/6mx (adm6996m/mx) initialization process is done, this pin is used to select using eeprom interface or sdc/sdio interface. eecs/ifsel interface 0 b , sdc/sdio interface 1 b , eeprom interface eecs o 4 ma, pd, lvttl eeprom chip select during samurai-6m/6mx (adm6996m/mx) initialisation, this pin is used as eeprom chip select signal. during samurai-6m/6mx (adm6996m/mx) initialize itself, samurai-6m/6mx (adm6996m/mx) will drive eeprom interface signal to read settings from eeprom. any other devices attached to eeprom interface should drive hi- z or keep tristate during this period. see chapter 3.4.2 eeprom interface for more details. 81 xoven i pd, lvttl cross over enable value on this pin (active low) will be latched by samurai- 6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) for port 4~0 crossover auto detect (only available in tp interface). note: power on setting. 0 b , disable 1 b , enable eesk i/o 4 ma, pd, lvttl eeprom serial clock during samurai-6m/6mx (adm6996m/mx) initialisation, this pin is used to output clock to eeprom. after samurai- 6m/6mx (adm6996m/mx) initialization process is done, this pin is used as eeprom interface clock input if ifsel = 1. sdc i pd, lvttl serial management interface clock input if ifsel = 0, this pin is used as serial management interface clock input. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 26 rev. 1.31, 2005-11-25 79 led_mode i pd, lvttl enable mac to choose led display mode value on this pin will be latched by samurai-6m/6mx (adm6996m/mx) at the rising edge of resetl( rc ) as single/dual color led mode control signal. see chapter 3.1.12 led display for more details. note: power on setting. edi i/o 8 ma, pd, lvttl eeprom serial data input during samurai-6m/6mx (adm6996m/mx) initialize itself, this pin is used to output address and command to access eeprom. after the initialization process is done, this pin becomes an input pin to monitor eeprom data if ifsel = 1. sdio i/o 8 ma, pd, lvttl serial management interface data input/output if ifsel = 0, this pin is used as data input/output pin of serial management interface. power/ground, 48 pins 4, 5, 12, 13, 20, 27, 28, 34, 35 gnda gnd ? ground used by ad block 1, 9, 17, 24, 38 vcca2 pwr ? 1.8 v, power used by tx line driver 8, 16, 23, 31 vccad pwr ? 3.3 v, power used by ad block 126 gndbias gnd ? ground used by bias block 128 vccbias pwr ? 3.3 v, power used by bias block. 123 gndpll gnd ? ground used by pll 122 vccpll pwr ? 1.8 v, power used by pll 45, 64, 76, 83, 93, 118 gndik gnd ? ground used by digital core 46, 75, 82, 94, 116 vccik pwr ? 1.8 v, power used by digital core 50, 70, 87, 99, 108 gndo gnd ? ground used by digital pad 49, 71, 88, 109 vcc3o pwr ? 3.3 v, power used by digital pad miscellaneous 41 test i pd, lvttl test mode reserved and should keep 0 when normal operation. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 27 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx interface description 86 cfg0 i pu, lvttl configuration 0 combined with p4_busmd0 and p4_busmd1 , samurai- 6m/6mx (adm6996m/mx) provides 3 bus type for port 4. {cfg0, p4_busmd[1:0]}, bus mode of port 4 0_00 b , phy interface 0_01 b , mac mii 1_xx b , pcs mii 69 wait_init i pd, lvttl wait initialization this pin will be used to pause all activities after power up until eeprom is loaded successfully or cpu initialization is done.. 0 b , pause until loading eeprom is done. 1 b , pause until eeprom successfully loaded or cpu initialization is done. 65 int_n o od,8 ma interrupt active low interrupt signal to indicate the status change in the interrupt status register. interrupt signal will keep active low until host read the status of isr register. 0 b , interrupt 1 b , not interrupt 40 mdio i/o 8 ma, pd, lvttl management data mdio transfers management data in and out of the device synchronous to mdc. 44 mdc i pd, st management data reference clock a non-continuous clock input for management usage. samurai-6m/6mx (adm6996m/mx) will use this clock to sample data input on mdio and drive data onto mdio according to rising edge of this clock. 85 cko25m o 8 ma, pd, lvttl 25m clock output free running 25m clock output (even during power on reset) 119 rc i st rc input for power on reset this pin is sampled by using the 25 mhz free running clock signal which gets the input from xi to generate the low- active reset signal, resetl. see chapter 5.3.2 power on reset for the timing requirements. 120 xi ai ana 25mhz crystal /oscillator input 25mhz crystal or oscillator input. variation is limited to +/- 50ppm. 121 xo ao ana 25mhz crystal output when connected to oscillator, this pin should be left unconnected. 127 rtx ai ana constant voltage reference external 1.0 k ? 1% resistor connection to ground. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
samurai-6m/mx adm6996m/mx interface description data sheet 28 rev. 1.31, 2005-11-25 125 vref ai ana analog reference voltage used by internal bias circuit for voltage reference. external 0.1uf capacitor connection to ground for noise filter. 124 control ai/o ana fet control signal the pin is used to control fet for 3.3 v to 1.8 v regulator. external 0.1uf capacitor connection to ground for noise filter, even the pin is un-connected. table 3 io signals (cont?d) pin or ball no. name pin type buffer type function
data sheet 29 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3 function description 3.1 switch functional description the samurai-6m/6mx (adm6996m/mx) uses the ?store & forward? switching approach for the following reasons: 1. store & forward switches allow switching between different speed media (e.g. 10basex and 100basex). such switches require large elastic buffers, especially when bridging between a server on a 100 mbit/s network and clients on a 10 mbit/s segment 2. store & forward switches improve overall network performance by acting as a ?network cache? 3. store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (fcs) before forwarding to the destination port 3.1.1 basic operation the samurai-6m/6mx (adm6996m/mx) receives incoming packets from one of its ports, uses the source address (sa) and fid to update the address table, and then forwards the packet to the output ports determined by the destination address (da) and fid. if the da and fid are not found in the address table, the samurai-6m/6mx (adm6996m/mx) treats the packet as a broadcast packet and forwards the packet to the other ports within the same group. the samurai-6m/6mx (adm6996m/mx) can automatically learn the port number of attached network devices together with the sa and fid of all the incoming packets. if the sa and fid are not found in the address table, the samurai-6m/6mx (adm6996m/mx) adds it to the table. 3.1.2 buffers and queues the samurai-6m/6mx (adm6996m/mx) incorporates 6 transmit queues and receive buffer areas for the 6 ethernet ports. the receive buffers, as well as the transmit queues, are located within the samurai-6m/6mx (adm6996m/mx) along with the switch fabric. the buffers are divided into 192 blocks of 256 bytes each. the queues of each port are managed according to each port?s read/write pointer. input buffers and output queues are maintained through proprietary patent pending unique (universal queue management) scheme. 3.1.3 full duplex flow control when a full duplex port runs out of its receive buffers, a pause command will be issued by samurai-6m/6mx (adm6996m/mx) to notify the packet sender to pause transmission. this frame based flow control is totally compliant to ieee 802.3x. when the flow control hardware pin ( gfcen ) is set to high, during power on reset, and per port pause is enabled, samurai-6m/6mx (adm6996m/mx) will output and accept 802.3x flow control packets. 3.1.4 half duplex flow control back-pressure is supported for half-duplex operation. when the samurai-6m/6mx (adm6996m/mx) cannot allocate a receive buffer for the incoming packet (buffer full), the device will transmit a jam pattern on the port, thus forcing a collision. 3.1.5 back-off algorithm the samurai-6m/6mx (adm6996m/mx) implements the truncated exponential back off algorithm compliant to the 802.3 standard. samurai-6m/6mx (adm6996m/mx) will restart the back off algorithm by choosing 0-9 collision
samurai-6m/mx adm6996m/mx function description data sheet 30 rev. 1.31, 2005-11-25 count. after 16 consecutive retransmit trials, the samurai-6m/6mx (adm6996m/mx) resets the collision counter. users can set the back off (see 0010 h , bd ) to disable this function. 3.1.6 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the value is 9.6 s for 10 mbit/s ethernet and 960 ns for 100 mbit/s fast ethernet. for the receive end, samurai-6m/6mx (adm6996m/mx) is designed to tolerate ipg gaps greater than 64 bits. for the transmit end, samurai-6m/6mx (adm6996m/mx) will always transmit packets with the minimum ipg gap equal to 96 bits. if users want to shorten the transmission ipg gap, users can enable the short ipg function (see 000b h , tsie ). then samurai-6m/6mx (adm6996m/mx) will instruct its output mac to transmit packets in average 92 bits ipg gap. 3.1.7 trunking function samurai-6m/6mx (adm6996m/mx) supports only one trunking port. if port 3 and port 4 trunk (see 000b h , te ) function is enabled, samurai-6m/6mx (adm6996m/mx) will treat port 3 and port 4 as the same port to make the bandwidth equal to 200m. when any of these two ports link fail, the samurai-6m/6mx (adm6996m/mx) will automatically change the transmit path from the failed link port to linked one. output port based load balancing is implemented in samurai-6m/6mx (adm6996m/mx), without any users? setting. 3.1.8 illegal frames the samurai-6m/6mx (adm6996m/mx) will discard all illegal packets. these packets are 1. undersized packets: the packets received with the length of less than 64 bytes are discarded 2. oversized packets: the packets received with the length of more than ?maxpktlen? bytes are discarded. see (0011 h , mpl ) to see how to set the maxpktlen value 3. crc packets: the packets received with a wrong fcs value are discarded 4. symbol error packets: the packets received with symbol error are discarded 5. source violation packets: the packets received with a source violation could be discarded in some cases. see ( source violation ) description. 6. vlan violation packets: the frames received with a vlan violation can be discarded in some cases. see ( vlan violation ) description 3.1.9 broadcast storm samurai-6m/6mx (adm6996m/mx) allows users to limit the traffic of the broadcast address (da = ffffffffffff h ) to prevent them from blocking the switch bandwidth. if users also want to limit the multicast packets(da[40] = 1 b ), they can set the multicast packet counted into storming counter (see 0010 h , mp ) function. two threshold and storm enable bits (see 003b h and 003c h , storm_en , storm_100_th , storm_10_th ) are used to control the broadcast storm. 1. time scale. samurai-6m/6mx (adm6996m/mx) uses 50ms on a scale to meter the storm packets. 2. storm keeps on at least 1.6 seconds if any of the ports meet the rising threshold in the 4 consecutive 50 ms intervals. in these 1.6 seconds, the ports meet the rising threshold and will start to discard the broadcast or multicast packets until the 50 ms interval expires. users could also disable input filter (see 000b h , if ) function to forward above packets to the un-congested port instead of discarding directly. 3. storm finishes. after the 1.6-second storm period, samurai-6m/6mx (adm6996m/mx) will check the port that makes the storm on. if all of these ports meet the falling threshold in the 2 consecutive 50 ms intervals and no parameter rising threshold falling threshold all link ports are 100m 100m threshold (see 003b h ) 1/2 100m threshold not all link ports are 100m 10m threshold (see 003c h ) 1/2 10m threshold
data sheet 31 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description other ports meet the rising threshold at the same time, samurai-6m/6mx (adm6996m/mx) will treat it the storm has finished. 3.1.10 bandwidth control samurai-6m/6mx (adm6996m/mx) supports hardware-based bandwidth control for both ingress and egress traffic. ingress and egress rate can be limited independently on each port base. the samurai-6m/6mx (adm6996m/mx) uses 8 ms on the scale, and the minimum bandwidth control unit is 64 kbit/s so users can configure the rate equal to k * 64 kbit/s, 1 <= k <= 2048. samurai-6m/6mx (adm6996m/mx) maintains two counters (input and output) for each port. for example, if users want to limit rate equal to 64 kbit/s, they should configure the bandwidth control threshold equal to 1. at each time unit, samurai-6m/6mx (adm6996m/mx) will add 64 to the counter and decrease the byte length when receiving a packet in this period. when the counter is decreased to zero, we can divide the control behavior into two parts: for the ingress control, the ingress port will not receive packets any more. if flow control is enabled, pause packets will be transmitted, if back pressure is enabled, jam packets will be transmitted, and if the above functions are not enabled, the packets will be discarded. for the egress control, the egress port will not transmit any packets, so the egress bandwidth is controlled. samurai-6m/6mx (adm6996m/mx) allows users to control the ingress and egress bandwidth at the same time (see 0033 h , bandwidth control enable register ). for example, set p0 receive bandwidth control to 6 mbit/s 1. set the receive bandwidth of p0. n= {r0bw_th3, r0bw_th2, r0bw_th1, r0bw_th0, 6?b0} = 0x005e 2. enable p0 receive bandwidth control. set 0033 h [0]=1 3.1.11 smart discard the samurai-6m/6mx (adm6996m/mx) supports a smart mechanism to discard packets early according to their priority to prevent the resource blocked by the low priority. the discard ratio is as follows: 3.1.12 led display three leds per port are provided by samurai-6m/6mx (adm6996m/mx): link/act, duplex/col and speed. the dual-color led mode is also supported by samurai-6m/6mx (adm6996m/mx). for easy production purpose, the test signal is sent to each led at power on reset stage. the led display mode is controlled by: 1. dual-color-ee (see 0012 h ): it is an eeprom register to control the dual or single color mode. it is useless when the value (wait_init) on the pin wait_init is low. table 4 smart disacrd queue discard mode queue 3 discard mode of queue 3 in 0010 h [15:14] queue 2 discard mode of queue 2 in 0010 h [13:12] queue 1 discard mode of queue 1 in 0010 h [11:10] queue 0 discard mode of queue 0 in 0010 h [9:8] table 5 discard ratio discard mode 00 01 10 11 utilization 00 0% 0% 0% 0% utilization 01 0% 0% 25% 50% utilization 11 0% 25% 50% 75%
samurai-6m/mx adm6996m/mx function description data sheet 32 rev. 1.31, 2005-11-25 2. led_mode : it is the value latched on the edi pin during the power on reset. it?s also used to control the dual or single color mode and is useless when the value (wait_init) is high. 3. led-enable (see 0012 h ): when cpu is attached and this cpu has no ability to pull the edi to high or low, users may set the wait_init to high to delay the led test, write the correct value to the dual-color-ee , write 1 b into register led-enable , and then the led test starts. 4. dup_col_sep (see 0012 h ): dupcol leds indicate the duplex status only. 5. dhcol_led_en (see 0030 h ): when enabled, pin dupcol0 shows col_10m status and pin dupcol1 shows col_100m status. these two leds are necessary in the dual-speed hub. 3.1.12.1 single color led display table 6 single color led display pin name status lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 these pins have no power on reset values on them, and samurai-6m/6mx (adm6996m) uses active low value to drive the led. so the output values of these pins after the power on reset are shown as follows: 1. first period: this period lasts 1.28 s for led on test. samurai-6m/6mx (adm6996m/mx) drives value 0 to open the led. 2. second period: this period lasts 0.48 s for led off test. samurai-6m/6mx (adm6996m/mx) drives value 1 to close the led. 3. normal period: this period indicates the link status. 0 b , port links up and led is on. 1 b , port links down and led is off. 0/1 b , port links up and is transmitting or receiving. the led flashes at 10 hz. ldspd4/ldspd3/ ldspd2/ldspd1/ ldspd0 the behavior of these pins is the same as the lnkact, except for the normal period. normal period: this period indicates the speed status. 0 b , port links up and its speed is 100m. led is on. 1 b , port links down or its speed is 10m. led is off.
data sheet 33 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description dupcol2/ dupcol1/ dupcol0 these 3 pins have power on reset values on them. samurai-6m/6mx (adm6996m/mx) needs to consider these values to drive the correct value. if the power on reset value is value_power_on, then the display is as follows: 1. first period: this period lasts 1.28 s for led on test. samurai-6m/6mx (adm6996m/mx) drives ~value_power_on to open the led. 2. second period: this period lasts 0.48 s for led off test. samurai-6m/6mx (adm6996m/mx) drives value_power_on to close the led. 3. normal period: this period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led flashes at 10 hz. 0/1 b , port links up and collision is detected. the led flashes at 10 hz. if dup_col_sep is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b , this value is cancelled. led doesn?t blink. if dhcol_led_en is enabled, the display in the normal period is as follows: dupcol0: 10m collision indicator. 0/1 b , one of the ports links up in 10m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = when the above event is not satisfied, the led is off. dupcol1: 100 m collision indicator. 0/1 b , one of the ports links up in 100m half-duplex mode and detects a collision event. the led flashes at 20 hz. value_power_on = the above event is not satisfied. led is off. dupcol4/ dupcol3 the behavior of these pins is the same as the lnkact, except the normal period. normal period: this period indicates the duplex/collision status. ~value_power_on = port links up in the full-duplex mode. led is on. value_power_on = port links down. led is off. 0/1 b , port links up and collision is detected. the led flashes at 10 hz. if dup_col_sep is enabled, the normal period changes its way to display. ~value_power_on = port links up in the duplex mode. led is on. value_power_on = port links down or links up in the half-duplex mode. led is off. 0/1 b , this value is cancelled. led doesn?t blink. table 6 single color led display (cont?d) pin name status
samurai-6m/mx adm6996m/mx function description data sheet 34 rev. 1.31, 2005-11-25 3.1.12.2 dual color led display users should be careful that dupcol led only supports the single color mode. the only difference between single and dual color for dupcol led is the self-test time. 3.1.12.3 circuit for single led mode figure 3 circuit for single color led mode table 7 dual color led display pin name status (lnkact4, ldspd4)/ (lnkact3, ldspd3) (lnkact2, ldspd2) (lnkact1, ldspd1) (lnkact0, ldspd0) first period: test led on with green color. it lasts 1.28 s. 01 b , led is on with green color. second period: test led on with yellow color. it lasts 1.28 s. 10 b , led is on with yellow color. third period: test led off. 00 b , led is off. normal period: this period shows the status of the link and speed at the same time. 00 b , port links down.led is off. 11 b , port links down. led is off. 01 b , port links up in 100m. led glows green. 10 b , port links up in 10m. led glows yellow. 0/1,1 b , port links up in 100m and is receiving or transmitting. led blinks with green color at 10 hz. 0/1,0 b , port links up in 10m and is receiving or transmitting. led blinks with yellow color at 10 hz. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 the behavior of these pins is the same as the single mode, except the self-test period. the led on test period is 2.56 s instead of 1.28 s. dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0/ lnkact4/lnkact3 lnkact2/lnkact1 lnkact0/ l d spd 4/ l d spd 3 l d spd 2/ l d spd 1 l d spd 0/ dupcol2/dupcol1/ dupcol0 3.3v 0v
data sheet 35 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.12.4 circuit for dual led mode figure 4 circuit for dual color led mode 3.1.13 packet identification packets are classified to determine if they should be passed to the cpu port or another entity for special handling. table 8 packet identification packets identified by samurai- 6m/6mx (adm6996m/mx) comments bpdu the ethernet destination address is 01 80 c2 00 00 00 h . pause the ethernet destination address is 01 80 c2 00 00 01 h . ether-type field is 8808 h . opcode is 0001 h . slow the ethernet destination address is 01 80 c2 00 00 02 h . pae the ethernet destination address is 01 80 c2 00 00 03 h . reser_r0 the ethernet destination address ranges between 01 80 c2 00 00 04 h and 01 80 c2 00 00 0f h . reser_r1 the ethernet destination address ranges between 01 80 c2 00 00 10 h and 01 80 c2 00 00 1f h . gxrp the ethernet destination address ranges between 01 80 c2 00 00 20 h and 01 80 c2 00 00 22 h . reser_r2 the ethernet destination address ranges between 01 80 c2 00 00 23 h and 01 80 c2 00 00 2f h . reser_r3 the ethernet destination address ranges between 01 80 c2 00 00 30 h and 01 80 c2 00 00 ff h . rarp the ethernet destination address is ff ff ff ff ff ff h and the ether-type field is 8035 h . arp the ethernet destination address is ff ff ff ff ff ff h and the ether-type field is 8036 h . igmp_ip the ethernet destination address is 01 00 5e xx xx xx h . ether-type field is 0800 h (ip). ip version is 4 and the protocol field is 02 h (igmp). mld_ip ethernet destination address is 33 33 xx xx xx xx h . the ether-type field is 0800 h (ip). ip version is 6 and the protocol field is 3a h (icmp). mld_ipv6 ethernet destination address is 33 33 xx xx xx xx h . the ether-type field is 86dd h (ip). ip version is 6 and the protocol field is 3a h (icmp). l d spd 4/ l d spd 3/ l d spd 2/ l d spd 1/ ldspd0 lnkact4/lnkact3/ lnkact2/lnkact1/ lnkact0 3.3v 0v dupcol4/dupcol3/ dupcol2/dupcol1/ dupcol0 dupcol2/dupcol1/ dupcol0
samurai-6m/mx adm6996m/mx function description data sheet 36 rev. 1.31, 2005-11-25 for learning purpose, samurai-6m/6mx (adm6996m/mx) sometimes divides ethernet address into three groups. 3.1.13.1 span packet samurai-6m/6mx (adm6996m/mx) supports 4 spanning tree port state (disable, blocking/listening, learning and forwarding state) for every port to enable spanning tree protocol function when co-operates with an external cpu. these port states are defined in stps of eeprom register 0013 h ~ 0018 h . samurai-6m/6mx (adm6996m/mx) supports a function to specify a packet to be treated as a span packet. beside disable state, the span packets will not be dropped by spanning tree port state settings. 3.1.13.2 management packet samurai-6m/6mx (adm6996m/mx) reserves some buffers for these packets, so they are not dropped because of traffic congestion. management packets are never limited by the bandwidth control, stormed by the storming control, or dropped due to smart discard function. others type the ether-type field matches one of the type filters. protocol the protocol field matches one of the protocol filters. tcpudp the tcp/udp port number matches one of the tcp/udp filters. mac_ctrl the ether-type field is 8808 h , but opcode is not 0001 h . table 9 packet identification groups packets identified by samurai- 6m/6mx (adm6996m/mx) comments multicast the first bit of the ethernet destination address is 1, but not all 1. broadcast the ethernet destination address is ff ff ff ff ff ff h . unicast the first bit of the ethernet destination address is 0. table 10 span packet packet type description bpdu / slow / pae / reser_r0 / reser_r1 / gxrp / reser_r2 / reser_r3 the span packet is determined in priority order by: 1. span bit defined in the special tag, when span_valid is set. 2. span bit defined in the learning table when there is a match for da+fid. 3. span bit defined in the control table when there is a match for da. 4. span bit in register 003e h . arp / rarp the span packet is determined in priority order by: 1. span bit defined in the special tag, when span_valid is set. 2. span bit in register 000d h . igmp_ip / mld_ip / mld_ipv6 the span packet is determined in priority order by: 1. span bit defined in the special tag, when span_valid is set. 2. span bit in register 000c h . others the span packet is determined in priority order by: 1. span bit defined in the special tag, when span_valid is set. 2. span bit defined in the learning table when there is a match for da+fid.if the first and second conditions are not satisfied, the frame is classified as non-span packets. table 8 packet identification (cont?d) packets identified by samurai- 6m/6mx (adm6996m/mx) comments
data sheet 37 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.13.3 cross_vlan packet cross-vlan packets are defined to cross vlan boundary or bypass the vlan violation. table 11 management packet packet type description bpdu / slow / pae / reser_r0 / reser_r1 / gxrp / reser_r2 / reser_r3 the management packet is determined in priority order by: 1. management bit defined in the special tag, when management_valid is set. 2. management bit defined in the learning table when there is a match for da+fid. 3. management bit defined in the control table when there is a match for da. 4. management bit in register 003e h . arp / rarp the management packet is determined in priority order by: 1. management bit defined in the special tag, when management_valid is set. 2. management bit in register 000d h . igmp_ip / mld_ip / mld_ipv6 the management packet is determined in priority order by: 1. management bit defined in the special tag, when management_valid is set. 2. management bit in register 000c h . others the management packet is determined in priority order by: 1. management bit defined in the special tag, when management_valid is set. 2. management bit defined in the learning table when there is a match for da+fid.if the first and second conditions are not satisfied, the frame is classified as non-management packets. table 12 cross_vlan packet packet type description bpdu / slow / pae / reser_r0 / reser_r1 / gxrp / reser_r2 / reser_r3 the cross-vlan packet is determined in priority order by: 1. cross_valn bit defined in the special tag, when cross_vlan_valid is set. 2. cross_vlan bit defined in the learning table when there is a match for da+fid. 3. cross_vlan bit defined in the control table when there is a match for da. 4. cross_vlan bit in register 003e h . arp / rarp the cross_vlan packet is determined in priority order by: 1. cross_vlan bit defined in the special tag, when cross_vlan_valid is set. 2. cross-vlan bit in register 000d h .
samurai-6m/mx adm6996m/mx function description data sheet 38 rev. 1.31, 2005-11-25 3.1.14 tagged vlan or port vlan the difference between two vlan rules is the way to search the vlan boundary. users could enable ?tag base vlan? (see 0011 h , tbv ) bit to instruct samurai-6m/6mx (adm6996m/mx) to operate in the tagged vlan mode. 3.1.14.1 vlan filters samurai-6m/6mx (adm6996m/mx) supports 16 vlan filters, each specifying a valid bit, a tag pri, a vid, a fid, a tagged member, and a member. 3.1.14.2 port vlan port vlans are created by grouping individual physical ports together. in this mode, only 6 vlan filters (vlan filter 0 ~5) are used. by the time examining the received frame, the source port is used as an index to search the vlan filter. if the source port is port 0, then member in the filter 0 is the vlan group that port 0 joins. 3.1.14.3 tagged vlan tagged vlan is created with the aid of the vid in the packet or vid assigned by the source port. this vid is compared with 16 vids in the vlan filters to check if any match exists. the member in this matched filter is the vlan boundary for the packet. 3.1.14.4 vid for comparison and carried through samurai-6m/6mx (adm6996m/mx) vid for comparison and carried through samurai-6m/6mx (adm6996m/mx) (as egress vid) depends on the vlan configuration. vid0: the incoming packet is tagged with vid = 000 h . enable ?replace vid0? (see 000a h , rvid0 ) to replace the null vid with pvid (see basic control registers) if necessary. vid1: the incoming packet is tagged with vid = 001 h . enable ?replace vid1? (see 000a h , rvid1 ) to replace vid1 with pvid (see basic control registers) if necessary. vidfff: the incoming packet is tagged with vid = fff h . enable ?replace vidfff? (see 000a h , rvidfff ) to replace vidfff with pvid (see basic control registers) if necessary. igmp_ip / mld_ip / mld_ipv6 the cross_vlan packet is determined in priority order by: 1. cross-vlan bit defined in the special tag, when cross_vlan_valid is set. 2. cross-vlan bit in register 000c h . others the cross_vlan packet is determined in priority order by: 1. cross_vlan bit defined in the special tag, when cross_vlan_valid is set. 2. cross_vlan bit defined in the learning table when there is a match for da+fid.if the first and second conditions are not satisfied, the frame is classified as non-cross_vlan packets. table 13 vlan filters vlan filter 0 vlan_valid vlan_pri[2: 0] vid[11:0] fid[3:0] tagged member[5:0] member[5:0] ~ vlan filter 15 table 12 cross_vlan packet (cont?d) packet type description
data sheet 39 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description vlan security samurai-6m/6mx (adm6996m/mx) ignores packet?s vid and always uses pvid to see if there is a match and transfers it to the output ports. disables the ?vlan security disable? (see 0022 h , vsd ) to achieve this goal. input force no tag when enabled (see 0020 h , ifnte ), samurai-6m/6mx (adm6996m/mx) assumes all the packets are untagged and pvid is used. input force no tag and vlan security are different in some situations. 3.1.14.5 admit only vlan-tagged packets samurai-6m/6mx (adm6996m/mx) supports a function to check if the packet is vlan-tagged, and any packets received on that port that carries no vid (untagged packets or packets with vid = 0) are discarded and recorded as a vlan violation. this feature is implemented by programming the ?admit only vlan-tagged? (see 0027 h , aovtp ). samurai-6m/6mx (adm6996m/mx) assumes all the packets are untagged in the ?input force no tag? mode and users should care that in this situation, ?admit only vlan tagged? is of no effect. 3.1.14.6 vid check in tagged vlan, the vid for comparison must be contained in the vlan filters, or the packet received on the port will be dropped and recorded as a vlan violation. this feature is disabled by programming the ?vid check? bit to 0 (see 0026 h , vc ) to forward these packets instead of dropping them. 3.1.14.7 fid and vlan boundary in samurai-6m/6mx (adm6996m/mx), every incoming packet is associated with a fid group. samurai-6m/6mx (adm6996m/mx) searches the learning table for the fid + da, fid + sa. vlan boundary restricts the allowable destination ports. table 14 vid comparison parameter tagged frame with vid = 12?hfff packet transmitted tagged vlan security the frame is recorded as a vlan violation and discarded if vidfff is not replaced. output packets have only one vlan tag. input force no tag the frame is recognized as an untagged frame. pvid is carried with this packet to the output port. output packets may have double tags, because the packet is transmitted with an additional tag with pvid. table 15 fid search algorithm port vlan the source port number is the vlan filter index. we can find fid in this filter. tagged vlan vid match fid is contained in the matched filter. we can find fid in this filter. vid un- match vid check the frame is dropped. vid uncheck default fid is the fid (see 000a h , dfid ). if users configure samurai- 6m/6mx (adm6996m/mx) to back to port vlan (see 0027 h , bpv ), we can find the fid in the same way as the port vlan. when this feature is enabled, vlan filter 0 ~ 5 are for port vlan purpose and vlan filter 6 ~15 are for vid comparison. table 16 vlan boundary search algorithm port vlan the source port number is the vlan filter index. we can find the boundary in this filter.
samurai-6m/mx adm6996m/mx function description data sheet 40 rev. 1.31, 2005-11-25 3.1.14.8 ingress filter if the source port is not contained in the vlan boundary associated with the incoming packet, then this frame is dropped and recorded as a vlan violation. this feature is disabled by setting the ?ingress filter? (see 0021 h , ife ) bit to 0 b . 3.1.14.9 vlan violation when packets are recorded as a vlan violation packet, samurai-6m/6mx (adm6996m/mx) will drop them. the only way to ignore these violations is to classify these packets as cross_vlan packets. 3.1.14.10 txtag carried through samurai-6m/6mx (adm6996m/mx) each packet during receive is assigned 2-bit txtag value. this value is carried by samurai-6m/6mx (adm6996m/mx) to the output ports to help to determine if egress tagged is necessary. 3.1.14.11 tagged member carried through samurai-6m/6mx (adm6996m/mx) if the output port is a tagged port it is determined by the port or the vid. ports in the tagged members should egress packets tagged. tagged vlan vid match member is contained in the matched filter. we can find the boundary in this filter vid un- match vid check the frame is dropped. vid uncheck samurai-6m/6mx (adm6996m/mx) uses default vlan portmap as the boundary (see 003a h , dvm ). if users configure samurai-6m/6mx (adm6996m/mx) to ?back to port vlan? (see 0027 h , bpv ), we can back to find the boundary in the same way as the port vlan. when this feature is enabled, vlan filter 0 ~ 5 are for port vlan purpose and vlan filter 6 ~15 are for vid comparison. table 17 txtag carried through samurai-6m/6mx (adm6996m/mx) packet type description bpdu/slow/pae/reser_r0/ reser_r1/gxrp/reser_r2/ reser_r3 the txtag is determined in priority order by: 1. txtag in special tag with txtag_valid enabled. 2. txtag in the learning table when there is a match for da+fid in the learning table. 3. txtag in the control table when there is a match for da in the control table. 4. txtag defined in register 003e h . arp/rarp the txtag is determined in priority order by: 1. txtag in special tag with txtag_valid enabled. 2. txtag is defined in 000d h . igmp_ip/mld_ip/mld_ipv6 the txtag is determined in priority order by: 1. txtag in special tag with txtag_valid enabled. 2. txtag is defined in 000c h . other the txtag is determined in priority order by: 1. txtag in special tag with txtag_valid enabled. 2. the da + fid matches an entry in the learning table with txtag defined.if the first and second conditions are not satisfied, txtag is 2?b00. table 16 vlan boundary search algorithm (cont?d)
data sheet 41 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description users should note that when the special tag with tagged member valid = 1 b is incoming, the samurai-6m/6mx (adm6996m/mx) always uses tagged member in the special tag as the tagged member. 3.1.14.12 egress tag rule on the receiving port, samurai-6m/6mx (adm6996m/mx) will attach each packet with the tagged members by the ingress rule. when the packet reaches the destination port, samurai-6m/6mx (adm6996m/mx) will check if the destination port is a tagged member, if yes, the packet will be transmitted tagged. first way: new transmit tag disable (see 0x000ah) the ?output packet tagging? bit in the basic control registers determines the tagged members. second way: new transmit tag enable (see 0x000ah) port vlan the source port number is the vlan filter index. we can find the tagged member in this filter. tagged vlan vid match tagged members are contained in the matched vlan filter. we can find the tagged members in this filter vid un- match vid check the frame is dropped. vid uncheck samurai-6m/6mx (adm6996m/mx) uses the first way to determine the tagged members. if users configure samurai-6m/6mx (adm6996m/mx) to ?back to port vlan? (see 0027 h , bpv ), it can go back to find the tagged members in the same way as the port vlan. table 18 egress tag result untagged packets are received (if input force no tag is enabled, samurai-6m/6mx (adm6996m/mx) assumes all the received packets are untagged.) output port is in the tagged members carried with the packet. txtag description 00 b , system default tag. packets are transmitted tagged. 01 b , unmodified. packets are transmitted untagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged. output port is not in the tagged members carried with the packet. txtag description 00 b , system default tag. packets are transmitted untagged. 01 b , unmodified. packets are transmitted untagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged. output port is configured to operate in the bypass mode. see 002a h . txtag description 00 b , system default tag. packets are transmitted untagged. 01 b , unmodified. packets are transmitted untagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged.
samurai-6m/mx adm6996m/mx function description data sheet 42 rev. 1.31, 2005-11-25 3.1.14.13 tagged pri carried thr ough samurai-6m/6mx (adm6996m/mx) tagged packets are received. output port is in the tagged members carried with the packet. txtag description 00 b , system default tag. packets are transmitted tagged. 01 b , unmodified. packets are transmitted tagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged. output port is not in the tagged members carried with the packet. txtag description 00 b , system default tag. packets are transmitted untagged. 01 b , unmodified. packets are transmitted tagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged. output port is configured to operate in the bypass mode. see 002a h . txtag description 00 b , system default tag. packets are transmitted tagged. 01 b , unmodified. packets are transmitted tagged. 10 b , always tagged. packets are transmitted tagged. 11 b , always untagged. packets are transmitted untagged table 19 tagged pri carried untagged packets are received (if input force no tag is enabled, samurai- 6m/6mx (adm6996m/mx) assumes all the received packets are untagged.) port vlan [change priority enable, change rule] (see 000a h , pce & pcr ) 0x b , reverse pri. 10 b , vlan_pri field in the matched vlan filter. 11 b , reverse pri tagged vlan vid unmatch reverse pri vid match [change priority enable, change rule] (see 000a h , pce & pcr ) 0x b , reverse pri. 10 b , vlan_pri field in the matched vlan filter. 11 b , reverse pri table 18 egress tag result (cont?d)
data sheet 43 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.14.14 cfi carried through samurai-6m/6mx (adm6996m/mx) 3.1.14.15 egress tag egress tag contains egress pri, egress cfi, and egress vid. when packets are transmitted tagged, this egress tag associated with ethernet-type = 8100 h is inserted following the ethernet source address. egress pri: egress pri is tagged pri carried through samurai-6m/6mx (adm6996m/mx) from the source port. egress cfi: egress cfi is cfi carried through sa murai-6m/6mx (adm6996m/mx) from the source port. egress vid: egress vid is vid carried through samurai-6m/6mx (adm6996m/mx) from the source port. 3.1.15 priority queue samurai-6m/6mx (adm6996m/mx) supports 4 priority queues and each is assigned a weight. tagged packets are received. port vlan [change priority enable, change rule] (see 000a h , pce & pcr ) 0x b , tagged pri = the 3-bit user priority in the tag header. 10 b , vlan_pri field in the matched vlan filter. 11 b , reverse pri tagged vlan vid un- match change priority enable (see 000a h , pce ) 0 b , tagged pri = the 3-bit user priority in the tag header. 1 b , reverse pri. vid match [change priority enable, change rule] (see 000a h , pce & pcr ) 0x b , tagged pri = the 3-bit user priority in the tag header. 10 b , vlan_pri field in the matched vlan filter. 11 b , reverse pri reserve pri is reversed from the priority queue the packet is switched through. compare = queue, queue, queue, queue} xor vlan priority map in 000e h . then we get tagged pri. compare tagged pri xxxx_xxx0 b = 000 b xxxx_xx01 b = 001 b xxxx_x011 b = 010 b xxxx_0111 b = 011 b xxx0_1111 b = 100 b xx01_1111 b = 101 b x011_1111 b = 110 b 0111_1111 b = 111 b 1111_1111 b = 000 b table 20 cfi carried cfi carried untagged frames received (if input force no tag is enabled, samurai-6m/6mx (adm6996m/mx) assumes all the received packets are untagged.) cfi carried = 0 b tagged frame received cfi carried = original cfi in the tag header. table 19 tagged pri carried (cont?d)
samurai-6m/mx adm6996m/mx function description data sheet 44 rev. 1.31, 2005-11-25 3.1.15.1 system pri the system pri is determined in the order as follows: 1. (da+fid) was found in the learning table, then lrn_pri field (when lrn_prien is set) in this entry indicates the priority queue. 2. port pri in basic control register indicates the priority queue, when port_prien is enabled on that port. 3. the user priority field in the tag header is used for a tagged packet (?input force no tag? doesn?t effect samurai-6m/6mx (adm6996m/mx) to extract the pri in the tag header), when ?vlan priority? is enabled. the user priority in the tag header is a 3 bits field, samurai-6m/6mx (adm6996m/mx) uses ?vlan priority map? to map the priority queue. 4. for ip packets with no tag header, ip pri is used when ?service priority? (see 001f h ) is enabled. even for a tagged packet with ip header, we can set ?ip over vlan? (see basic control registers) bit to 1 to force using ip pri. three kinds of ip pri are available. a) for ipv6 packets with ip version = 6 h , the most significant 6 bits of the traffic class in the ipv6 header is used to map the priority queue by the service mapping registers. b) for ipv4 packets with ip version = 4 h , the most significant 3 bits of the tos field in the ipv4 header is used to map the priority queue by the tos priority map register. c) if ?tos using? (see 000a h ) is disabled, even for ipv4 packets, samurai-6m/6mx (adm6996m/mx) uses the most significant 6 bits of the tos field to map the priority queue by the service mapping registers. 5. if the packet matches the tcp/udp filters, the pri associated with this filter indicates the priority queue when ?tcp/udp prien? is set to 1 (see 0098 h ). users could enable ?tcpudp over ip? to force using the tcpudp pri when there is a match. 3.1.15.2 queue assigned table 21 priority queue queue weight queue 0 weight = 1 queue 1 weight = ?queue 1 weight? bits in 0025 h queue 2 weight = ?queue 2 weight? bits in 0026 h queue 3 weight = ?queue 3 weight? bits in 0027 h table 22 queue assigned packets identified by samurai- 6m/6mx (adm6996m/mx) the order of priority assigned bpdu/slow/pae/reser_r0/ reser_r1/gxrp/reser_r2/ reser_r3 1. the pri field with pri_valid = 1 in the special tag indicates the priority queue. 2. if (da+fid) matches an entry in the learning table, then lrn_pri field with lrn_prien enabled in this entry indicates the priority queue. 3. use pri in 003d h to indicate the queue the frame was switched. arp/rarp 1. the pri field with pri_valid = 1 in the special tag indicates the priority queue. 2. use pri in 000d h to indicate the priority queue when enabled. 3. use system pri.
data sheet 45 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description igmp_ip/mld_ip/mld_ipv6 1. the pri field with pri_valid = 1 in the special tag indicates the priority queue. 2. use pri in 000c h to indicate the priority queue when enabled. 3. use system pri. others 1. the pri field with pri_valid = 1 in the special tag indicates the priority queue. 2. use system pri. table 22 queue assigned (cont?d) packets identified by samurai- 6m/6mx (adm6996m/mx) the order of priority assigned
samurai-6m/mx adm6996m/mx function description data sheet 46 rev. 1.31, 2005-11-25 3.1.15.3 configure samurai qos function figure 5 to configure samurai qos function 3.1.16 address learning samurai-6m/6mx (adm6996m/mx) provides two ways to create the entry in the address table: dynamic learning and manual learning. a four-way hash algorithm is implemented to allow the maximum of 4 different addresses with the same hash key to be stored at the same time. up to 2k entries can be created and all entries are stored in the internal ssram. samurai-6m/6mx (adm6996m/mx) searches the learning table for the sa+fid of the incoming packet or the instruction from cpu. when both fields (a single sa may exist in different fid) are matched, there is a match. packet is received from the port entity port entity is the cpu port ? yes no no special tag pri_valid=1 ? take special tag pri field as priority yes (da+fid) matches? yes address entry lrn_prien=1 ? take address lrn_pri field as priority yes no no port_prien=1 ? yes take address port_pri field as priority no vlan priority enable ? take vlan priority map as priority no ip over tcp/udp =0 ? service priority enable ? yes take 3-bit tos priority map as priority no tos using ? 3-bit 6-bit take 6-bit service priority map as priority tcp/udp prien=1 ? yes tcp/udp action/filter yes take address port_pri field as priority no port priority enable in basic control register[7] port priority in basic control register[9:8] vlan priority enable in 0x1e[14:9] ip over vlan pri in basic control register[6] vlan priority map in 0x0e[15:0] ip over vlan pri =0 ? yes yes service priority enable in 0x1f[14:9] tos using 3-bit/6-bit in 0x0a[1] 6-bit service priority map in 0x6c ~ 0x73 3-bit tos priority map in 0x0f[15:0] tcp/udp prien in 0x98[5:0] ip over tcp/udp in 0x98[11:6] tcp/udp filter in 0x8c ~ 0x93 tcp/udp action in 0x96 ~0x98 campare tcp/udp source port or destination port in 0x98[13:12]
data sheet 47 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.16.1 dynamic learning the samurai-6m/6mx (adm6996m/mx) searches for sa and fid of an incoming packet in the address table and takes dynamic learning action as follows: 1. if (sa+fid) was not found in the learning table, create a new entry with sa, fid, and the incoming port. 2. if (sa+fid) was found in the learning table, and the incoming port and the portmap doesn?t match, create a new entry with sa, fid, and the incoming port. dynamic learning will be disabled in the following condition: 1. security violation exists on the port. 2. vlan violation exists on the port. 3. the packet is a pause packet. 4. the number of the addresses that port has learned has reached its maximum. 5. the port disables its learning function (see extended control registers). 6. the packet is an illegal packet (too long, too short or fcs error). 7. a packet with special tag is received and the lrn bit is 0 and lrn_valid = 1 b . 8. the port is in the disabled state in the spanning tree protocol. 9. the port is in the blocking/listening state in the spanning tree protocol. 10. all the four entries in the same hash address are occupied and all of them are static addresses. 3.1.16.2 manual learning the samurai-6m/6mx (adm6996m/mx) implements the manual learning through the cpu?s help. the cpu can create or remove any entry in the address table. each entry could be static. ?static? means the entry will not be aged forever. when the entry is static, then the definition in some fields is modified to make samurai-6m/6mx (adm6996m/mx) work more flexibly. 3.1.16.3 learning table 3.1.16.3.1 entry format in the learning table 69 68 67 66 ? 58 57 ? 52 51 ? 48 47 ? 0 bad info_type occupy info_ctrl/age timer portmap fid address field description bad the entry is marked to show if it is failed during the learning table memory bist time. 0 b , don?t fail 1 b , fail info_type static address. 0 b , the entry is not static 1 b , the entry is static occupy the entry is marked to show the status if the entry is occupied. 0 b , don?t occupy 1 b , occupy
samurai-6m/mx adm6996m/mx function description data sheet 48 rev. 1.31, 2005-11-25 3.1.16.3.2 the registers accessing the learning table 12 registers are provided by samurai-6m/6mx (adm6996m/mx) to support access to the address table. these 12 registers are address table control register 0 ~ 5 and address table status register 0 ~ 5 in 011a h ~ 0125 h . info_ctrl/age timer info_ctrl is used when the entry is static. bit description 8 source intrusion 0 b , it isn?t a violated source address 1 b , it is a violated source address 7 span 0 b , not a span packet 1 b , a span packet 6 management 0 b , not a management packet 1 b , a management packet 5 cross_vlan 0 = not a cross_vlan packet. 1 = a cross_vlan packet. 4:3 txtag it is used as an option for inserting tag on the transmission port. 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged 2 lrn_prien 0 b , lrn_pri is not used 1 b , lrn_pri is used 1:0 lrn_pri it identifies the address priority. 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 age timer is used when the entry is not static. bit description 8:0 age timer this timer is used to control the ageing time. portmap the field is used as the output ports associated with the fid+mac address. fid the field is used as the fid group associated with the mac address. address the mac address in the learning table. table 23 control register description for accessing the address table command access control info_type info_ctrl/age timer portmap fid address control 5[6:4] control 5[3:0] control 4[12] control 4[8:0] control 3[9:4] control 3[3:0] {control 2, control 1, control 0} field description
data sheet 49 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description the address, fid, portmap, info_ctrl/age timer and info_type in the control register have the same meaning as those in the entry format. the command and access control are described as follows: table 24 description for command and access control command access control description 000 b 0111 b create a new address 000 b 1111 b overwrite an existed address 001 b 1111 b erase an existed address 010 b 0000 b search an empty address 010 b 1001 b search by the port in the output port field 010 b 1010 b search by the forwarding group specified in the forwarding group field 010 b 1100 b search by the address specified in the mac address field 010 b 1110 b search by the address and forwarding group 010 b 1101 b search by the address and output port 010 b 1011 b search by the forwarding group and the output port 010 b 1111 b search by the address, the forwarding group and the output port 011 b 0100 b initial to location by the address field 011 b 0000 b initial to the first address table 25 status register description busy result bad occupy info_type info_ctrl/ age_time portmap fid address status 5 [15] status 5 [14:12] status 5 [2] status 5 [1] status 5 [0] status 4 [8:0] status 3 [9:4] status 3 [3:0] {status 2, status 1, status 0} table 26 description for the status register address if the search operation is successful, the switch will return the mac address in this field. if the search fails, this field doesn't mean anything. fid if the search operation is successful, the switch will return fid in the matched entry. portmap if the search operation is successful, the switch will return portmap in the entry. info_ctrl/ age time if the search operation is successful, the switch will return info_ctrl/age timer in the entry. info_type if the search operation is successful, the switch will return info_type in the entry occupy if the search operation is successful, the switch will return occupy in the entry bad if the search operation is successful, the switch will return bad in the entry
samurai-6m/mx adm6996m/mx function description data sheet 50 rev. 1.31, 2005-11-25 3.1.16.3.3 rules to access the learning table 1. check the busy bit in the status register to see if the access engine is available. if the engine is busy, wait until the engine is free. if the engine is available, go to the following step. 2. write the mac address[15:0] into the control register 0. 3. write the mac address[31:16] into the control register 1. 4. write the mac address[47:32] into the control register 2. 5. write the portmap and fid into the control register 3. 6. write the info_ctrl/age timer and info_type into the control register 4. 7. write the access control and command into the control register 5 to define the operation. 8. wait for the engine to complete (check the busy bit). 9. read the desired result returned in the status register. note: before a new search starts, the cpu should execute the ?initial command? to initial the search pointer. the search engine could search the aim from the top to the bottom. the search engine has an ability to move the pointer to the associated location automatically (the result will be returned). because more than one entry may match the searching condition (by port, by address, etc.) at the same time, the cpu should continue to restart the search engine until the command result = entry not is found to confirm that no other matching entries exist and at this time a new search can be started. result this field tells us the status for not only the search operation but also the creating operation. 000 b , command ok 001 b , all entry used. this result happens only for the create operation. samurai-6m/6mx (adm6996m/mx) uses the 4-way address lookup engine so it allows 4 different addresses stored at each hash location. if these 4 entries are all static, then cpu will not successfully create 5 different addresses hashed to the same location and 001 will be returned. the only way to create 5 different addresses is to remove one of earlier addresses. 101 b , command error busy this bit indicates if the table engine for access is available. 1 b , the engine is busy and it will not accept the command from the cpu. 0 b , the engine is available. table 26 description for the status register (cont?d)
data sheet 51 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.16.3.4 example 3.1.17 address aging samurai-6m/6mx (adm6996m/mx) maintains an age timer for each address. the aging timer is reset to 0 when the packet is received. when aging time counts up to 300 seconds, it means that station didn?t transmit packets in this period and the address can be removed from the table. this could help to prevent a station which leaves the network and occupies a table space for a long time. aging function can be disabled from the eeprom (see extend control registers) and if the address is static, then samurai-6m/6mx (adm6996m/mx) will not age it out either. the default aging timer is 300 seconds. user could change aging timer select (0011 h , ats ) to shorten the aging time. 3.1.18 hardware based igmp snooping samurai-6m/6mx (adm6996m/mx) supports igmp v1/v2 snooping without any software effort. samurai-6m/6mx (adm6996m/mx) will monitor the igmp traffic and update its embedded igmp membership table if the hardware example rule the user needs samurai- 6m/6mx (adm6996m/mx) to forward the specified unicast packet (da = 0012- 3456-789a h and fid = 2) to port 3 forever. 1. check the busy bit. if busy = 0 b , go to the next step. if busy = 1 b , wait. 2. write 789a h into control register 0. 3. write 3456 h into control register 1. 4. write 0012 h into control register 2. 5. write 0082 h into control register 3. 6. write 1000 h into control register 4. 7. write 0007 h into control register 5. 8. read the status register 5 to check the busy bit. if busy = 0 b , check the command result to see if the create operation is successful. if busy = 1 b , wait the user needs samurai- 6m/6mx (adm6996m/mx) to forward the specified multicast packet (da = 0123-4567-89ab h and fid = 3) to port 0, and port 1 both. this address could be aged. 1. check the busy bit. if busy = 0 b , go to the next step. if busy = 1 b , wait. 2. write 89ab h into control register 0. 3. write 3456 h into control register 1. 4. write 0123 h into control register 2. 5. write 0033 h into control register 3. 6. write 0000 h into control register 4. 7. write 0007 h into control register 5. 8. read the status register 5 to check the busy bit. if busy = 0 b , check the command result to see if the create operation is successful. if busy = 1 b , wait the user wants to know how many stations attached to port 4 1. check the busy bit. if busy = 0 b , go to the next step. if busy = 1 b , wait. 2. write 0030 h into control register 5 to initial the search pointer to the first address. 3. wait until the busy bit changes to 0 b . 4. write 0100 h into the control register 3. 5. write 0029 h into the control register 5 to start the operation of the search by port. 6. read the status register 5 to check the busy bit. if busy = 0 b , check the command result to see if the search operation is successful (the mac address attached to port 4 could be derived from the mac address in the status register). if busy = 1 b , wait for completion. 7. if command result = ?command ok?, it means some other mac addresses attached to port 4 may exist. we should restart the ?search by port? command again to let the search engine look after another addresses. 8. if the command result = ?entry not found?, it means no other addresses attached to port 4 exist.
samurai-6m/mx adm6996m/mx function description data sheet 52 rev. 1.31, 2005-11-25 based igmp snooping function is enabled. ip multicast frames can be forwarded according to the port-map information of the membership table. the data of the membership can also be accessed by the cpu via sdc/sdio interface. the following registers could be used to configure the igmp snooping behavior. 1. eeprom register 00b h bit [13:12], additional snooping control register.ports. 2. eeprom register 00b h bit [2], source violation over snooping. 3. eeprom register 00b h bit [1], source violation over default. 4. eeprom register 00c h bit [13:6], various snooping control registers. 5. eeprom register 00c h bit [2], hardware igmp packet ignore cpu port. 6. eeprom register 00c h bit [1], hardware igmp snooping enable. 7. eeprom register 00c h bit [0], hardware igmp default router enable. 8. eeprom register 00d h bit [14], ip multicast packet treated as cross vlan packet. 9. eeprom register 01b h bit [14:9], multicast port-map. 10. eeprom register 03f h bit [15:8], query interval. 11. eeprom register 03f h bit [7:6], robust variable. 12. eeprom register 03f h bit [5:0], default router port-map. 3.1.18.1 entry format of igmp membership table 3.1.18.2 the registers accessing the igmp membership table the registers for accessing the igmp membership table are the same with accessing mac address filtering table, but the data format are re-defined as below. 57 56 55 ... 48 47 ? 42 41 ? 30 29 28... 23 22 ... 0 bad occupy reserved reserved reserved reserved portmap group id field description bad the entry is marked to show if it is failed during the memory bist time of igmp membership table. 0 b , doesn?t fail 1 b , fail occupy the entry is marked to show the status if the entry is occupied. 0 b , empty entry 1 b , occupied entry reserved reserved. ignore the content in reading and fill in 0 in writing. reserved reserved. ignore the content in reading and fill in 0 in writing. reserved reserved. ignore the content in reading and fill in 0 in writing. reserved reserved. ignore the content in reading and fill in 0 in writing. portmap this flag is used to denote whether the port is the member of this group or not. 0 b , the port is not the member of this group. 1 b , the port is the member of this group. group id ip multicast group id. table 27 control register description for accessing the igmp membership table command entry address entry data control 5[6:4] control 4[4:0] {control 3[9:0], control 2, control 1, control 0}
data sheet 53 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description the command used to access igmp membership table is defined as below.: 3.1.18.3 igmp snooping introduction igmp snooping is a feature that allows the switch to ?listen in? on the igmp conversation between hosts and routers. when a switch hears an igmp report from a host for a given multicast group, the switch adds the host's port number to the gda (group destination addresses) list for that group. and, when the switch hears an igmp leave, it removes the host's port from the multicast table entry. multicast address 1. multicast ip addresses are class d ip addresses. therefore, all ip addresses from 224.0.0.0 to 239.255.255.255 are multicast ip addresses. they are also referred to as group destination addresses (gda). 2. for each gda there is an associated mac address. this mac address is formed by 01-00-5e, followed by the last 23 bits of the gda translated in hex. therefore: ? 230.20.20.20 corresponds to mac 01-00-5e-14-14-14 ? 224.10.10.10 corresponds to mac 01-00-5e-0a-0a-0a consequently, this is not a one-to-one mapping, but a one-to-many mapping: ? 224.10.10.10 corresponds to mac 01-00-5e-0a-0a-0a ? 226.10.10.10 corresponds to mac 01-00-5e-0a-0a-0a, as well 3. some multicast ip addresses are reserved for special use. for example: ? 224.0.0.1 - all multicast-capable hosts. ? 224.0.0.2 - all multicast-capable routers ? 224.0.0.5 and 224.0.0.6 is used by: open shortest path first (ospf). in general, addresses from 224.0.0.1 to 224.0.0.255 are reserved and used by various protocols. igmp igmp is a standard defined in rfc1112 for igmpv1 and in rfc2236 for igmpv2. it specifies how a host can register a router to receive specific multicast traffic. igmpv1 ? membership query are issued by router at regular intervals to check whether there is still a host interested in the gda in that segment. table 28 description for command and access control command description 100 b write data into internal igmp table 101 b read data from internal igmp table table 29 entry format of igmp membership table busy result entry address entry data status 5[15] status 5[14:12] status 4[4:0] {status 3[9:0], status 2, status 1, status 0} table 30 ipv4/igmp/general query da 01005e000001 sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 224.0.0.1 unused (len*4-20) bytes tp 8?h11 unused 3 bytes ga 32?b0
samurai-6m/mx adm6996m/mx function description data sheet 54 rev. 1.31, 2005-11-25 ? membership report is issued by hosts that want to receive a specific multicast group (gda). host membership reports are issued either unsolicited (when the host wants to receive gda traffic first) or in response to a membership query. host membership queries are sent by router to the all multicast address: 224.0.0.1. these queries use 0.0.0.0 in the igmp gda field. a host for each group must respond to that query or the router will stop forwarding the traffic for that gda to that segment (after 3 attempts). the router simply keeps a multicast routing entry for each source and links it to a list of outgoing interfaces (interface from where the igmp report came). after three igmp query attempts with no answer, this interface is erased from outgoing interface list for all entries linked to that gda. note: igmpv1 has no leave mechanism. if a host no longer wants to receive the traffic, it simply quits. if it is the last, the router will not have any answers to its query and will delete the gda for that subnet. igmpv2 ? membership query ? igmpv1 membership report ? igmpv2 membership report ? leave group when a host wants to leave a group, it should send a leave group igmp message to destination 224.0.0.2 (instead of leaving silently like in igmpv1) table 31 ipv4/igmp/v1 report da 01005exxxxxx sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 4 bytes unused (len*4-20) bytes tp 8?h12 unused 3 bytes ga 4 bytes table 32 ipv4/igmp/general query da 01005e000001 sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 224.0.0.1 unused (len*4-20) bytes tp 8?h11 unused 3 bytes ga 32?b0 table 33 ipv4/igmp/v1 report da 01005exxxxxx sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 4 bytes unused (len*4-20) bytes tp 8?h12 unused 3 bytes ga 4 bytes table 34 ipv4/igmp/v2 report da 01005exxxxxx sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 4 bytes unused (len*4-20) bytes tp 8?h16 unused 3 bytes ga 4 bytes
data sheet 55 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description ? group-specific query a router can now send a group-specific query by sending a membership query to the group gda instead of sending it to 0.0.0.0 learning the router port the switch listens to the following messages in order to detect router ports with igmp snooping ? igmp membership query send to 01-00-5e-00-00-01 once a router port is detected, it is added to the port list of all gdas in that vlan. [hardware igmp snooping] 1. enable hardware igmp snooping, set eeprom register 0c h [1]=1 2. hardware igmp default router ? if eeporm register 0c h [0]=0, samurai will learn the router port automatically. note: the presence of the router port is configured by query interval (eeprom register 3f h [15:8]) defined as the length of time that must pass before the router port decides there is no longer another multicast router which should be the querier. ? if eeporm register 0c h [0]=1, samurai will learn the router port according to the default router port-map. ? if eeprom register 3f h [5:0], default router port-map note: the router port always exists even no igmp query is received. the group membership is maintained by robust variable (eeprom register 3f h [7:6]) defined as the amount of query that must pass before the default router decides there are no members of a group on a network. joining a group with igmp snooping below are two joining scenarios. scenario a: host a is the first host to join a group in the segment. ? host a sends an unsolicited igmp membership report. ? the switch intercepts the igmp membership report that sent by the host that wanted to join the group. ? the switch creates a multicast entry for that group and links it to the port on which it has received the report and to all router ports. ? the switch forwards the igmp report on to all router ports. this is so that the router will also receive the igmp report and will update its multicast routing table accordingly. [hardware igmp snooping] table 35 ipv4/igmp/v2 leave da 01005000002 sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 224.0.0.2 unused (len*4-20) bytes tp 8?h17 unused 3 bytes ga 4 bytes table 36 ipv4/igmp/group-specific query da 01005exxxxxx sa 6 bytes type 16?h0800 ver 4?h4 len 4 bits tos 1 byte unused 7 bytes protocol 8?h02 unused 6 bytes dip 4 bytes unused (len*4-20) bytes tp 8?h11 unused 3 bytes ga 4 bytes
samurai-6m/mx adm6996m/mx function description data sheet 56 rev. 1.31, 2005-11-25 samurai supports 32 igmp membership table. samurai will maintain igmp membership table according to igmpv1/v2 protocol. if 32 igmp membership table is full, the later incoming igmp packets will follow ?multicast port-map?. user can use address table control register command and address table status register command to access 32 igmp membership table. ? igmp membership table read command ? (1) check the busy bit in the status register 5 [15] to see if the access engine is available. if busy = 1 b , wait until the engine is free. if busy = 0 b , go to the following step. ?(2) write control register 4 [4:0] to assign the entry numbers you want to access. ?(3) write control register 5 [6:4] = 101 b to start the operation of read command. ? (4) read the busy bit in the status register 5 [15] to see if the operation is successful. if busy = 1 b , wait until the operation is completed. if busy = 0 b , read status register 5 ~ 0 to get the igmp membership table entry. ? igmp membership table write command ? (1) check the busy bit in the status register 5 [15] to see if the access engine is available. if busy = 1 b , wait until the engine is free. if busy = 0 b , go to the following step. ?(2) write control register 0 ~ 4 to assign the entry numbers you want to access. ?(3) write control register 5 [6:4] = 100 b to start the operation of write command. ? (4) read the busy bit in the status register 5 [15] to see if the operation is successful. if busy = 1 b , wait until the operation is completed. if busy = 0 b , read status register 5 ~ 0 to get the igmp membership table entry. 3.1.19 source violation source violation is defined in samurai-6m/6mx (adm6996m/mx) to support flexible security modes. see security option in the eeprom basic register and the src_violation bit in the learning table. table 37 igmp membership table address table control 0 eeprom register 11a h address table status 0 eeprom register 120 h address table control 1 eeprom register 11b h address table status 1 eeprom register 121 h address table control 2 eeprom register 11c h address table status 2 eeprom register 122 h address table control 3 eeprom register 11d h address table status 3 eeprom register 123 h address table control 4 eeprom register 11e h address table status 4 eeprom register 124 h address table control 5 eeprom register 11f h address table status 5 eeprom register 125 h
data sheet 57 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description security mode description first lock samurai-6m/6mx (adm6996m/mx) locks the first sa+fid of packets received on the port. after the first (sa+fid) is locked, samurai-6m/6mx (adm6996m/mx) starts to check packets with different (sa+fid). 1. if the packets are not assigned as management, drop it (modify the forwarding algorithm) and record it as a source violation. 2. if the packets are management packets, and source violation (see 000b h , system control register 1 ) is configured to 1 b for different kinds of packets, then samurai- 6m/6mx (adm6996m/mx) modifies the forwarding algorithm to drop these packets. they are also recorded as a source violation. 3. if the packets are management packets and source violation is configured to 0 b , then samurai-6m/6mx (adm6996m/mx) doesn?t modify the forwarding algorithm. in this situation, we don?t record this case as a source violation. first link lock the first received packets will be locked as first lock. the difference is that the receiving port will not receive and learn packets any more after the port links down even if it links up again. a source violation is recorded as the first lock. if samurai- 6m/6mx (adm6996m/mx) modifies the forwarding algorithm it is still as the first lock. assign lock samurai-6m/6mx (adm6996m/mx) allows users to assign the locked sa+fid through cpu?s help instead of the first sa+fid. a source violation is recorded as the first lock. if samurai-6m/6mx (adm6996m/mx) modifies the forwarding algorithm it is still as the first lock. assign link lock samurai-6m/6mx (adm6996m/mx) allows users to assign the locked sa+fid through cpu?s help instead of the first sa+fid. the others are the same as the first link lock. discard unknown the ?unknown source address? means that (sa+fid) is not found in the learning table or even is found but portmap doesn?t match the incoming port. if ?unknown? packets are received, samurai-6m/6mx (adm6996m/mx) records the source violation as the first lock. the rule to modify the forwarding algorithm is still as the first lock. unknown to cpu this option is the same as ?discard unknown? except that if samurai-6m/6mx (adm6996m/mx) decides to modify the forwarding algorithm, it will forward the packets to the cpu port instead of dropping them. source intrusion if the incoming port receives the pac kets with sa, marked as source intrusion, we handle these packets in the following rule: 1. enabled source intrusion must (see 000b h , sim ) to instruct samurai-6m/6mx (adm6996m/mx) to modify the forwarding algorithm and record the source violation always. 2. if source intrusion must is not enabled, samurai-6m/6mx (adm6996m/mx) also modifies the forwarding algorithm and records the source violation when any non- management packets are received. 3. if source intrusion must is not enabled, samurai-6m/6mx (adm6996m/mx) also modifies the forwarding algorithm and records the source violation when management packets are received but source violation is configured to 1 b . 4. if source intrusion must is not enabled, samurai-6m/6mx (adm6996m/mx) doesn?t modify the forwarding algorithm and records the source violation when management packets are received and source violation is configured to 0 b . samurai-6m/6mx (adm6996m/mx) allows the users to redirect the packets to the cpu port instead of dropping it when they violate the source intrusion (see source intrusion action in 000b h , sia ).
samurai-6m/mx adm6996m/mx function description data sheet 58 rev. 1.31, 2005-11-25 samurai-6m/6mx (adm6996m/mx) supports stricter security protection. the port is disabled when there is a source violation. enable security option[3] to enable this feature. 3.1.20 packet forwarding samurai-6m/6mx (adm6996m/mx) identifies packet headers and transfers it from the incoming port to the destination ports. 3.1.20.1 control table samurai-6m/6mx (adm6996m/mx) provides a control table for user to control the forwarding algorithm of the da = 01 80 c2 00 00 00 h ~ da = 01 80 c2 00 00 2f h easily. this control table is defined in 0074 h ~ 008b h . 3.1.20.2 default output ports the default output ports that a packet is transferred to are determined in the following order. 1. the portmap in the special tag with portmap_valid = 1 is used as the output ports. 2. the portmap in the learning table is used as the output ports, when (da+fid) matches an entry in the learning table. 3. the portmap in the hardware igmp table is used as the output ports, when da matches an entry in the hardware igmp table and ?hardware igmp snooping? (see 000c h , hise ) is enabled. 4. ?broadcast portmap? (see 001a h , bp ) is used as the output ports, when the incoming packet is a broadcast packet. 5. ?multicast portmap? (see 001b h , mp ) is used as the output ports, when the incoming packet is a multicast packet. 6. ?unicast portmap? (see 0019 h , up ) is used as the output ports, when the incoming packet is a unicast packet. 3.1.20.3 forwarding algorithm table 38 forwarding algorithm packets identified by samurai- 6m/6mx (adm6996m/mx) algorithm bpdu/slow/pae/reser_r0/ reser_r1/gxrp/reser_r2/ reser_r3 if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else if ((da+fid) matches an entry in the learning table)), then use the portmap in the learning table as the output ports. else if (da matches an entry in the control table), then the output ports are the portmap in the table. else are the output ports are the intersection of the pass portmap (see 003d h new reserve address control register 0 and 003e h new reserve address control register 1 ) and the ?reserve portmap? in the eeprom (see 001c h , rp ) arp/rarp if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else if (arp/rarp is trapped), then use arp/rarp portmap as the output ports. else uses ?default output ports? as the output ports.
data sheet 59 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.21 802.1x security function samurai-6m/6mx (adm6996m/mx) supports flexible security modes to implement 802.1x security function. if ?unauthorized? packets are received, samurai-6m/6mx (adm6996m/mx) will forward the packets to the cpu port to secure the forwarding algorithm. the following chart shows the identification flow for the security. igmp_ip/mld_ip/mld_ipv6 if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else if (hardware igmp snooping is enabled), if (hardware igmp packet ignore cpu port is enabled), then forwards packets to multicast portmap but doesn?t forward to the cpu port. else forwards packets to multicast portmap. else if (igmp_ip/mld_ip/mld_ipv6 is trapped), then use igmp/igmp_ip/mld_ip/mld_ipv6 portmap as the output ports. else uses ?default output ports? as the output ports. type if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else uses type portmap as the output ports. protocol if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else uses protocol portmap as the output ports. tcpudp if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else uses tcpudp portmap as the output ports. mac_ctrl if (portmap_valid in the special tag is 1), then use portmap in the special tag as the output ports. else uses mac ctrl portmap as the output ports. others use ?default output ports? as the output ports table 38 forwarding algorithm (cont?d) packets identified by samurai- 6m/6mx (adm6996m/mx) algorithm
samurai-6m/mx adm6996m/mx function description data sheet 60 rev. 1.31, 2005-11-25 figure 6 flow chart of 802.1x security function packet is received from the port entity security port ? yes (sa+fid) is not found in the learning table ? no yes no port security option ? 010 001 discard unknown forward unknown to cpu dynamic learning cpu access mac address table manual learning forwarding security port in 0x11 ~ 0x18[14] security port in 0x11 ~ 0x18[13:11 ] if the entry is static and the portmap doesn?t include the incoming port, the packet will be discarded
data sheet 61 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.22 special tag special tag is inserted after the ethernet sa field allows the cpu to tell the switch how to handle the packets it sends or to know the source port when the cpu receives a packet. 3.1.22.1 special tag for the receive users are allowed to enable special tag receive (0011 h , stre ) function to instruct samurai-6m/6mx (adm6996m/mx) to check the special tag to see if this field contains any commands when packets are received on the cpu port. 8 bytes preamble 6 bytes da 6 bytes sa byte 0 special tag 0 byte 1 special tag 1 byte 2 special tag 2 byte 3 special tag 3 byte 4 special tag 4 byte 5 special tag 5 4 bytes vlan tag 6 bytes snap 2 bytes type/length data 4 bytes crc table 39 special tag for the receive special tag description byte 0 adm prefix 0. byte 1 adm prefix 1. when special tag receive is enabled, samurai-6m/6mx (adm6996m/mx) will compare {adm prefix -, adm prefix 1} with adm tag ether type (see 002e h , atet ). if they are different, special tag is ignored. if they are the same, samurai-6m/6mx (adm6996m/mx) uses the special tag to make switching decisions. byte 2 bit [7]: don?t care bit [6]: portmap_valid 1 b , valid 0 b , not valid bit [5:0]: portmap in the special tag
samurai-6m/mx adm6996m/mx function description data sheet 62 rev. 1.31, 2005-11-25 byte 3 bit [7]: span_valid 1 b , valid 0 b , not valid bit [6]: span 1 b , span packet 0 b , not span packet bit [5]: management_valid 1 b , valid 0 b , not valid bit [4]: management 1 b , management packet 0 b , not management packet bit [3]: cross_vlan_valid 1 b , valid 0 b , not valid bit [2]: cross_vlan 1 b , cross_vlan packet 0 b , not cross_vlan packet bit [1]: lrn_valid 1 b , valid 0 b , not valid bit [0]: lrn 1 b , learn 0 b , not learn byte 4 bit[7]: ignore bit[6]: pri_valid 1 b , valid 0 b , not valid bit[5:4]: pri 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 bit [3]: ignore bit [2]: txtag_valid 1 b , valid 0 b , not valid bit [1:0]: txtag byte 5 bit [6]: tagged member valid 1 b , valid 0 b , not valid bit [5:0]: tagged member, bit[x] = 1: port is in the tagged member table 39 special tag for the receive (cont?d) special tag description
data sheet 63 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.1.22.2 special tag for the transmit users are allowed to enable special tag transmit (0011 h , stte ) function to instruct samurai-6m/6mx (adm6996m/mx) to insert the special tag followed sa in the packets transmitted from the cpu port. samurai- 6m/6mx (adm6996m/mx) also allows users to choose what kinds of packets they don?t want to insert this special tag even when special tag transmit (0011 h , stte ) function is enabled. table 40 option for special tag transmit packets identified by samurai- 6m/6mx (adm6996m/mx) condition result bpdu/slow/pae/reser_r0/res er_r1/gxrp/reser_r2/reser_ r3 special tag transmit = 0 b . or{special tag transmit, insert reserve} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert reserve} = 11 b . insert special tag on the cpu port. arp/rarp special tag transmit = 0 b . or{special tag transmit, insert arp/rarp} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert arp/rarp} = 11 b . insert special tag on the cpu port. igmp_ip/mld_ip/mld_ipv6 special tag transmit = 0 b . or{special tag transmit, insert snoop} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert snoop} = 11 b . insert special tag on the cpu port. type special tag transmit = 0 b . or{special tag transmit, insert type} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert type} = 11 b . insert special tag on the cpu port. protocol special tag transmit = 0 b . or{special tag transmit, insert protocol} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert protocol} = 11 b . insert special tag on the cpu port. tcpudp special tag transmit = 0 b . or{special tag transmit, insert tcp/udp} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert tcp/udp} = 11 b . insert special tag on the cpu port. mac_ctrl special tag transmit = 0 b . or{special tag transmit, insert mac ctrl} = 10 b . don?t insert special tag on the cpu port. {special tag transmit, insert mac ctrl} = 11 b . insert special tag on the cpu port.
samurai-6m/mx adm6996m/mx function description data sheet 64 rev. 1.31, 2005-11-25 others special tag transmit = 0 b . or{special tag transmit, insert default, source violation} = 100 b . don?t insert special tag on the cpu port. {special tag transmit, insert default, source violation} = 110 b . or{special tag transmit, insert default, source violation} = 101 b .{special tag transmit, insert default, source violation} = 111 b . insert special tag table 41 special tag for the transmit special tag description byte 0 adm prefix 0. byte 1 adm prefix 1. byte 2 bit [7]: source violation. 1 = this packet is a source violated packet and its forwarding algorithm to the cpu port was modified . 0 = this packet is not a source violated packet.bit [6]: mirror. 1 = this is a mirrored packet. 0 = this is not a mirrored packet.bit [5]: span. 1 = this is a span packet. 0 = this is not a span packet.bit [4]: management. 1 = this is a management packet. 0 = this is not a management packet.bit [3]: ignore.bit [2:0]: source port. 000 b = port 0. 001 b = port 1. 010 b = port 2. 011 b = port 3. 100 b = port 4.101 b = port 5. byte 3 egress tag[15:8]. byte 4 egress tag[7:0]. byte 5 ignore. table 40 option for special tag transmit (cont?d) packets identified by samurai- 6m/6mx (adm6996m/mx) condition result
data sheet 65 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description 3.2 port4 and port5 mii connection in adm6996m/mx, there are 3 different configurations (normal phy, mac type mii and pcs type mii, cfg0 ) for port4. if port4 is configured in normal phy mode, then it is identical to port0~port3 and port4?s mii signals are ignored. if port4 is configured in mac type mii mode, it can be used for the homepna application and embedded single phy will not be used. in adm6996m/mx, the most popular is to configure port4 as the pcs type mii for the router?s wan port application. users can see figure 7 and figure 10 for more clear picture. for the port5, there are three different configurations (mac type mii mode, gpsi mode and rmii, p5_busmd0 ) for connecting to cpu?s mii/gpsi or rmii interface. here we dipicted two general router applications of adm6996m/mx, one is connected to cpu with single mii and another is connected to cpu with dual mii. in figure 7 , we can see either lan to wan or wan to lan, the packets will go through the same mii port. because the cpu need to send out the packets with the registered mac id to the wan port, and this mac id may also come in from the lan ports. we know the switch learning scheme can?t permit the packets with same mac id input from different ports. in the adm6996m/mx design, we use the mac clone and vlan group to solve this problem. from figure 10 , users can have more details for this implementation. figure 7 adm6996m/mx to cpu with single mii connection implementation of wan/lan applications on samurai adm6996m/mx implements wan/lan application by adm6996m/mx special tag functions. special tag is inserted after the ethernet sa field to allow the cpu to tell the switch how to handle the packets it sends or to know the source port when the cpu receives a packet. table 42 special tag pream- ble da sa special tag 0 special tag 1 special tag 2 special tag 3 special tag 4 special tag 5 vlan tag snap type/ length data crc 8b 6b 6b byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 4b 6b 2b 4b 6 port switch core cpu with single mii mii p0 phy p0 mac p1 phy p1 mac p2 phy p2 mac p3 phy p3 mac p4 phy p4 mac p5 mac lan ports wan port mac mii
samurai-6m/mx adm6996m/mx function description data sheet 66 rev. 1.31, 2005-11-25 step 1: set eeprom 11 h [12]=1 to enable special tag receive (cpu to adm6996m/mx). step 2: set eeprom 11 h [11]=1 to enable special tag transmit (adm6996m/mx to cpu). set eeprom 11 h [15:13] to assign cpu port number. default cpu port is "101 - port5". set eeprom 0b h [5] to set the option whether adm6996m/mx cpu port checks crc for the packet with special tag receive. set eeprom 11 h [10] to set the option whether adm6996m/mx adds special tag transmit to pause frame. the configurations are as follows. figure 8 the configurations of the implementation by adm6996m/mx special tag functions ? step 1: set adm6996m/mx to port-based vlan mode (default) ? step 2: set wan/lan group note: ? ? ? is necessary and ?o? is option to implement port-based vlan function of lan group. port 0, port 0/1/2/3/5, set reg 40 h to 002f h port 1, port 0/1/2/3/5, set reg 42 h to 002f h port 2, port 0/1/2/3/5, set reg 44 h to 002f h port 3, port 0/1/2/3/5, set reg 46 h to 002f h port 4, port 4/5, set reg 48 h to 0030 h port 5, port 0/1/2/3/4/5, set reg 4a h to 003f h table 43 set wan/lan group eeprom received port forwarding group port-based group port 0 port 1 port 2 port 3 port 4 port 5 40 h port 0 ? ooo ? 42 h port 1 o ? oo ? 44 h port 2 o o ? o ? 46 h port 3 ooo ?? 48 h port 4(wan port) ?? 4a h port 5(cpu port) ?????? cpu port 5 mii, untag, pvid=1 port 0 untag pvid=1 port 1 untag pvid=1 port 2 untag pvid=1 port 3 untag pvid=1 port 4 untag pvid=1 special tag transmit lan port wan port special tag receive
data sheet 67 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description ? step 3: set eeprom 11 h [12:11]="11" to enable special tag receive/transmit enable software operation: figure 9 software operation ? step 1: ? if untag packet received from lan port forwards to cpu port, adm6996m/mx will insert special tag followed sa in the packets transmitted from the cpu port. adm6996m/mx also allows users to choose what kinds of packets they don't want to insert this special tag in. table 44 packets identified by adm6996m/mx packets identified by adm6996m/mx condition (eeprom 0x11h[11] and 0x99h[8:0] result bpdu/slow/ pae/reser_r0/ reser_r1/ gxrp/ reser_r2/ reser_r3 special tag transmit = 0 b . or {special tag transmit, insert reserve} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert reserve} = 11 b insert special tag on the cpu port. arp/rarp special tag transmit = 0 b . or {special tag transmit, insert arp/rarp} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert arp/rarp} = 11 b . insert special tag on the cpu port. igmp_ip/mld_ip/ mld_ipv6 special tag transmit = 0 b . or {special tag transmit, insert snoop} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert snoop} = 11 b . insert special tag on the cpu port. cpu port 5 mii, untag, pvid=1 port 0 untag pvid=1 port 1 untag pvid=1 port 2 untag pvid=1 port 3 untag pvid=1 port 4 untag pvid=1 lan port wan port 1) untag packet 2) special tag with source port 3) cpu re-defines special tag 4) special tag packet with port map 5) untag packet
samurai-6m/mx adm6996m/mx function description data sheet 68 rev. 1.31, 2005-11-25 ? step 2: cpu must re-define the special tag for the receive to determine the destination group. ? step 3: if mac_clone function is enabled, cpu must set lrn parameter to disable learning mechanism for specific packet. in figure 10 , it shows an easy way to connect the cpu with dual mii for the routing application. in this application, port4?s embedded and isolated phy will be connected to the wan port. cpu will act as the bridge to translate the packet?s frame for lan/wan and use different mii to handle the packets either from lan to wan or from wan to lan. the isolated phy is helpful to reduce the bom cost. type special tag transmit = 0 b . or {special tag transmit, insert type} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert type} = 11 b . insert special tag on the cpu port. protocol special tag transmit = 0 b . or {special tag transmit, insert protocol} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert protocol} = 11 b . insert special tag on the cpu port. tcpudp special tag transmit = 0 b . or {special tag transmit, insert tcp/udp} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert tcp/udp} = 11 b . insert special tag on the cpu port. mac_ctrl special tag transmit = 0 b . or {special tag transmit, insert mac ctrl} = 10 b . don't insert special tag on the cpu port. {special tag transmit, insert mac ctrl} = 11 b . insert special tag on the cpu port. others special tag transmit = 0 b . or {special tag transmit, insert default, source violation} = 100 b . don't insert special tag on the cpu port. {special tag transmit, insert default, source violation} = 110 b . or {special tag transmit, insert default, source violation} = 101 b . {special tag transmit, insert default, source violation} = 111 b . insert special tag table 44 packets identified by adm6996m/mx (cont?d) packets identified by adm6996m/mx condition (eeprom 0x11h[11] and 0x99h[8:0] result
data sheet 69 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description figure 10 adm6996m/mx to cpu with dual mii connection normally, the mac mode mii should be connected to the phy mode mii. but in some applications, we need to connect both mac mode mii to each other as shown. in figure 10 , due to most cpu?s mii being mac mode, port4 is pcs to mac connection and port5 is mac to mac connection. through the hardware setting, it is easy to set adm6996m/mx port5 mii to be operating in 100m full duplex mode. and this kind mode (100m full) is normally the operation mode to be with cpu, the interface connection is described in the following diagram. (1) cko25m is the 25m clock driven out by adm6996m/mx to fit 100m mii operation. this clock output provides 8ma driving capability and it can directly connected to txclk/rxclk. (2) due to full duplex mode, so col is tied to gnd. 6 port switch core cpu with dual mii mii p0 phy p0 mac p1 phy p1 mac p2 phy p2 mac p3 phy p3 mac p4 phy lan ports wan port mii p4 pcs mii p5 mac mac mii
samurai-6m/mx adm6996m/mx function description data sheet 70 rev. 1.31, 2005-11-25 figure 11 100m full duplex mac to mac mii connection note: 1. pin 60 and pin 61 should be pull low to let p5_busmd be latched as ?00? and make port5 be operating in mii mode ( p5_busmd0 ). 2. pin 89 (spdtnp5) should be pull low or floating to set port5 be operating in 100mbit/s. 3. pin 91 (dphalfp5) should be pull low or floating to set port5 be operating in full duplex mode. 4. pin 90 (lnkfp5) should be pull low or floating to set port5 link up. about the pcs mode mii connecting to mac mode mii, it?s very straightforward. if pcs and mac follow the mii standard timing and users notice the pcb layout balance, it should not be an issue for pcs to connect to the mac. in figure 12 , we depicted this interface connection and described how to configure port4 as the pcs mode mii.
data sheet 71 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description figure 12 pcs to mac mii connection note: 5. from the cfg0 pin description, we know it needs to set {cfg0, p4_busmd[1:0]} as 1xx b to configure port4 be operating in pcs mode mii. so it doesn?t matter the value on p4_busmd[1:0] (pin 105 and pin 106) and we only pull high the cfg0 or make it floating (due to it has internally pull high) is ok. 6. pin 51 (spdtnp4) acts as duplex led for port 4; in half duplex mode, it is collision led for each port. 7. pin 107 (dphalfp4) used to indicate the speed status of port 4. 8. pin 92 (lnkfp4) used to indicate the link/activity status of port 4. 3.3 10/100m phy block the 100base-x section of the device implements the following functional blocks: 100base-x physical coding sub-layer (pcs) 100base-x physical medium attachment (pma) 100base-x physical medium dependent (pmd) the 10base-t section of the device implements the following functional blocks: 10base-t physical layer signaling (pls) 10base-t physical medium attachment (pma) the 100base-x and 10base-t sections share the following functional blocks: clock synthesizer module mii registers ieee 802.3u auto negotiation the interfaces used for communication between phy block and switch core is mii interface. auto mdix function is supported. this function can be enable/disabled by the hardware pin. the digital approach for the integrated phy of samurai-6m/6mx (adm6996m/mx) has been adopted.
samurai-6m/mx adm6996m/mx function description data sheet 72 rev. 1.31, 2005-11-25 3.3.1 auto negotiation the auto negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. for further details regarding auto negotiation, refer to clause 28 of the ieee 802.3u specification. the samurai-6m/6mx (adm6996m/mx) supports four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. the auto negotiation function within the samurai-6m/6mx (adm6996m/mx) can be controlled either by internal register access or by the use of configuration pins are sampled. if disabled, auto negotiation will not occur until software enables bit 12 in mii register 0. if auto negotiation is enabled, the negotiation process will commence immediately. when auto negotiation is enabled, the samurai-6m/6mx (adm6996m/mx) transmits the abilities programmed into the auto negotiation advertisement register at address 04h via flp bursts. any combination of 10 mbit/s, 100 mbit/s, half duplex, and full duplex modes may be selected. auto negotiation controls the exchange of configuration information. upon successfully auto negotiation, the abilities reported by the link partner are stored in the auto negotiation link partner ability register at address 05 h . the contents of the ?auto negotiation link partner ability register? are used to automatically configure to the highest performance protocol between the local and far-end nodes. software can determine which mode has been configured by auto negotiation by comparing the contents of register 04 h and 05 h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list. 100base-tx full duplex (highest priority) 100base-tx half duplex 10base-t full duplex 10base-t half duplex (lowest priority) the basic mode control register at address 0h provides control of enabling, disabling, and restarting of the auto negotiation function. when auto negotiation is disabled, the speed selection bit (bit 13) controls switching between 10 mbit/s or 100 mbit/s operation, while the duplex mode bit (bit 8) controls switching between full duplex operation and half duplex operation. the speed selection and duplex mode bits have no effect on the mode of operation when the auto negotiation enable bit (bit 12) is set. the basic mode status register at address 1h indicates the set of available abilities for technology types (bit 15 to bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). these bits are hardwired to indicate the full functionality of the samurai-6m/6mx (adm6996m/mx). the bmsr also provides status on: whether auto negotiation is complete (bit 5) whether the link partner is advertising that a remote fault has occurred (bit 4) whether a valid link has been established (bit 2) the auto negotiation advertisement register at address 4h indicates the auto negotiation abilities to be advertised by the samurai-6m/6mx (adm6996m/mx). all available abilities are transmitted by default, but writing to this register or configuring external pins can suppress any ability. the auto negotiation link partner ability register at address 05h indicates the abilities of the link partner as indicated by auto negotiation communication. the contents of this register are considered valid when the auto negotiation complete bit (bit 5, register address 1h) is set. 3.3.2 speed/duplex configuration the twelve sets of four pins listed in table 45 configure the speed/duplex capability of each channel of samurai- 6m/6mx (adm6996m/mx). the logic states of these pins are latched into the advertisement register (register
data sheet 73 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description address 4 h ) for auto negotiation purpose. these pins are also used for evaluating the default value in the base mode control register (register 0 h ) according to table 45 . in order to make these pins have the same read/write priority as software, they should be programmed to 11111111b in case user likes to update the advertisement register through software. 3.4 hardware, eeprom and smi interface for configuration three ways are supported to configure the setting in the samurai-6m/6mx (adm6996m/mx): (1) hardware setting (2) eeprom interface (3) smi interface. users can use the eeprom and smi interfaces combined with the cpu port to provide proprietary functions. four pins are needed when using these two interfaces. see figure 13 for the description. figure 13 interconnection between samurai-6m/6mx (adm6996m/mx), eeprom and cpu 3.4.1 hardware setting the samurai-6m/6mx (adm6996m/mx) provides some hardware pins, where values residing on will be strapped for the default setting during the power on or reset. table 45 speed/duplex configuration auto negotia tion (pin & eepro m) speed (pin & eepro m) duplex (pin & eepro m) auto negoti ation advertise capability para llel detect capability 100f 100h 10f 10h 100f 100h 10f 10h 1 11111110101 1 10101010101 1 01100110001 1 00100010001 0 1 1 0 1 ??????? 0 1 0 0 ?1 ?????? 0 0 1 0 ??1 ????? 0 0 0 0 ???1 ???? adm6996 eeprom(93c66) cpu eecs eesk edi edo
samurai-6m/mx adm6996m/mx function description data sheet 74 rev. 1.31, 2005-11-25 3.4.2 eeprom interface the eeprom interface is provided to easily configure the setting without the cpu?s help. because the eeprom interface is the same as the 93c66, it also allows the cpu to write the eeprom register and renew the 93c66 at the same time. after the power up or reset (default value from the hardware pins fetched in this stage), the samurai-6m/6mx (adm6996m/mx) will automatically detect the presence of the eeprom by reading the address 0 in the 96c66. if the value = 4154 h , it will load all the data in the 93c66. if not, the samurai-6m/6mx (adm6996m/mx) will stop loading the 93c66. the user also can pull down the edo to force the samurai-6m/6mx (adm6996m/mx) not to load the 93c66. the 93c66 loading time is around 30ms. then cpu should drive the high- z value in the eecs , eesk and edi pins in this period if existing the cpu to read or write the registers in the samurai-6m/6mx (adm6996m/mx). the eeprom interface needs only one write command to complete a ?write? operation to the samurai-6m/6mx (adm6996m/mx). if users would like to update the 93c66 at the same time, then three commands, write enable, write, and write disable, are needed to complete this operation (see 93c66 spec. for the reference). users should note that the eerpom interface only allows the cpu to write the eeprom register in the samurai-6m/6mx table 46 hardware setting setting name description gfcen global flow control enable. 0 b , flow control capability is depended upon the register setting in corresponding eeprom register 1 b , all ports flow control capability is enabled. sdio_md sdc/sdio mode selection. 0 b , 16 bits mode p5_busmd[1:0] port 5 bus mode selection bit 0. p5_busmd[1:0] ,interface 00 b , mii 01 b , gpsi 10 b , rmii 11 b , reserved and not allowed. {cfg0, p4_busmd[1:0]} bus mode of port 4 0_00 b , phy interface 0_01 b , mac mii 1_xx b , pcs mii bpen recommend back-pressure in half-duplex. 0 b , disable back-pressure. 1 b , enable back-pressure recanen recommend auto negotiation enable. only valid for twisted pair interface. programmed this bit to 1 has no effect to fiber port. 0 b , disable all tp port auto negotiation capability 1 b , enable all tp port auto negotiation capability xoven cross over enable. only available in tp interface. 0 b , disable 1 b , enable led_mode enable mac to choose led display mode. 0 b , single color led 1 b , dual color led
data sheet 75 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description (adm6996m/mx) and doesn?t support the read command. if the cpu sends out the read command, then 93c66 will respond with the value inside, instead of samurai-6m/6mx (adm6996m/mx). users should also note that one additional eesk cycle is needed between any continuous commands (read or write). (1) read 93c66 via the eeprom interface (index = 2, data = 1111 h ). (2) write eeprom registers in the samurai-6m/6mx (adm6996m/mx) (index = 2, data =16?h2222). power-on-sequence of samurai the following diagram shows the power-on-sequence of samurai. 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 0 d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 start opcode eeprom adress (index) dummy eecs(cpu) eesk(cpu) edi (cpu) edo (93c46) one more eesk is needed eeprom read operation data 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 start opcode eeprom adress (index) eecs(cpu) eesk(cpu) edi (cpu) one more eesk is needed eeprom write operation d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data
samurai-6m/mx adm6996m/mx function description data sheet 76 rev. 1.31, 2005-11-25 figure 14 the power-on-sequence of samurai set adm6996lc/fc pin59 sdio_md=1 to 16-bit smi mode. set adm6996i/m pin59 sdio_md=0(default) to 16-bit smi mode. timing diagram of rc, eecs and eesk (with correct signature eeprom) waveform 1: rc reset waveform 2: eecs waveform 4: eesk time = 0 3.3v/1.8v power is stable rc reset is low time = 60 ms rc reset is about 1.5~1.6v latch pin for power-on-value check signature match? no yes time = 60 ~ 100 ms load eeprom normal operation smi i/f eecs=h eecs=0 eeprom i/f the power-on-value on eesk pin will set xoven (auto-mdix) the power-on-value on eedi pin will set ledmode check signature 0x4154h eeprom master mode eecs:output eesk:output eedi:output eedo:input eeprom slave mode eecs:input eesk:input eedi:input 16-bit smi mode eesk to be mdc input eedi to be mdio input/output
data sheet 77 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description figure 15 timing diagram of rc, eecs and eesk (with correct signature eeprom) timing diagram of rc, eecs and eesk (without eeprom) waveform 1: rc reset waveform 2: eecs waveform 4: eesk
samurai-6m/mx adm6996m/mx function description data sheet 78 rev. 1.31, 2005-11-25 figure 16 timing diagram of rc, eecs and eesk (without eeprom) 3.4.3 smi interface the smi consists of two pins, management data clock ( eesk ) and management data input/output ( edi ). the samurai-6m/6mx (adm6996m/mx) is designed to support an eesk frequency up to 25 mhz. the edi pin is bi- directional and may be shared with other devices. eecs pin is needed to pull low if eeprom interface is also used. the edi pin requires a 1.5 k ? pull-up which, during idle and turnaround periods, will pull edi to a logic one state. samurai-6m/6mx (adm6996m/mx) requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset. the first 32 bits are preamble consisting of 32 contiguous logic one bits on edi and 32 corresponding cycles on eesk. following preamble is the start-of-frame field indicated by a <01 b > pattern. the next field signals the operation code (op): <10 b > indicates read from management register operation, and <01 b > indicates write to management register operation. the next field is the management register address. it is 10 bits wide and the most significant bit is transferred first. during read operation, a 2-bit turn around (ta) time spacing between the register address field and data field is provided for the edi to avoid contention. following the turnaround time, a 16-bit data stream is read from or written into the management registers of the samurai-6m/6mx (adm6996m/mx). (a) preamble suppression the smi of samurai-6m/6mx (adm6996m/mx) supports a preamble suppression mode. the samurai-6m/6mx (adm6996m/mx) requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset. this requirement is generally met by pulling-up the resistor of edi while the samurai-6m/6mx (adm6996m/mx) will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required.
data sheet 79 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx function description when samurai-6m/6mx (adm6996m/mx) detects that there is address match, then it will enable read/write capability for external access. when address is mismatched, then samurai-6m/6mx (adm6996m/mx) will tristate the edi pin. (b) read switch register via smi interface (offset hex = 10?h2, data = 16?h2600) (c) write switch register via smi interface (offset hex = 10?h180, data = 16?h1300) how to use samurai 16-bit mode smi to access eeprom/counter/phy register by cpu mdc/mdio interface samurai supports 16-bit mode smi interface to access eeprom/counter/phy register by cpu mdc/mdio interface. the smi interface consists of two pins, management data clock (eesk) and management data input/output (eedi). figure 17 smi interface ? the difference between smi command and mdc/mdio command table 47 (d) the pin type of eecs, eesk, edi and edo during the operation pin name reset operation load eeprom write operation read operation eecs input output input input eesk input output input input edi input output input input/output edo input input input input eesk edi(cpu) edi(adm6996i/m) z 0 1 1 0 0 0 0 0 0 0 0 0 1 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (read) register address (10'h2 in this example) ta register data (16'h2600 in this example) ~ ~ smi read operation one mor e eesk is needed eesk edi (cpu) z 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (write) register address (10'h180 in this example) ta register data (16'h1300 in this example) 0 ~ ~ smi write operation one mor e eesk is needed
samurai-6m/mx adm6996m/mx function description data sheet 80 rev. 1.31, 2005-11-25 ? samurai smi command uses 10-bit register address to access allocate eeprom/counter/phy register. memory map so you need to divide 10-bit register address to 5-bit phy address and 5-bit reg address of mdc/mdio command to access eeprom/counter register map. for samurai phy register map, you can set the 5-bit phy address = '10000' and use the standard reg address to access p0~p4 phy mii register. 3.5 the hardware difference between adm6996m/mx and adm6996f adm6996fc is a power-down version to replace adm6996f and adm6996m/mx is advanced function version for new applications. pin description(qfp128) table 48 memory map register definition 0000 h ~ 003f h eeprom baisc register map 0040 h ~ 009b h eeprom extended register map 00a0 h ~ 0143 h counter and switch status map 0200 h ~ 02ff h phy register map table 49 pin description(qfp128) pin no. adm6996m/mx adm6996f notes 59 p5txd3(sdio_md) p5txd3(vol23) for adm6996fc, sdio_md=0 default 32bit mode for adm6996m/mx, sdio_md=0 default 16bit mode add pull-up/down resistor for adm6996f/fc/m compatible design to avoid wrong power-on-latch. 60 p5txd2(rmiisel) p5txd2(romcode25 ) add pull down resistor for adm6996f/fc/m p5 mii mode to avoid wrong power-on-latch. 61 p5txd1(7wire) p5txd1(p5gpsi) add pull down resistor for adm6996f/fc/m p5 mii mode to avoid wrong power-on-latch. 65 int_n vccik(1.8v digital) interrupt for learning table access/port security/counter overflow/port status add a option design to cpu int_n pin
data sheet 81 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description 4 registers description the eeprom provides samurai-6m/6mx (adm6996m/mx) with many option settings main settings ? port configuration: speed, duplex, flow control capability and tag/ untag. ? vlan & tos priority mapping ? broadcast storming rate and trunk. ? fiber select, auto mdix select ? vlan mapping ? per port buffer number table 50 registers address space module base address end address note eeprom basic register map 0000 h 003f h eeprom extended register map 0040 h 009c h counter and switch status map 00a0 h 0143 h phy register map 0200 h 02ff h table 51 registers overview register short name register long name offset address page number sig signature register 00 h 91 p0bc p0 basic control register 01 h 91 p0ec p0 extended control register 02 h 93 p1ec p1 extended control register 02 h p1bc p1 basic control register 03 h p2ec p2 extended control register 04 h p3ec p3 extended control register 04 h p2bc p2 basic control register 05 h p4ec p4 extended control register 06 h p5ec p5 extended control register 06 h p3bc p3 basic control register 07 h p4bc p4 basic control register 08 h p5bc p5 basic control register 09 h sc0 system control register 0 0a h 94 sc1 system control register 1 0b h 95 ms multicast snooping register 0c h 97 ar arp/rarp register 0d h 99 vpm vlan priority map register 0e h 100 tpm tos priority map register 0f h 101 sc2 system control register 2 10 h 102 sc3 system control register 3 11 h 103
samurai-6m/mx adm6996m/mx registers description data sheet 82 rev. 1.31, 2005-11-25 sc4 system control register 4 12 h 104 p0so port 0 security option 13 h 106 p1so port 1 security option 14 h p2so port 2 security option 15 h p3so port 3 security option 16 h p4so port 4 security option 17 h p5so port 5 security option 18 h ufgpm unicast port map andforward group port map 19 h 107 bfgpm broadcast port map andforward group port map 1a h 108 mfgpm multicast port map and forward group port map 1b h 109 rfgpm reserve port map and forward group port map 1c h 110 piofgpm packet identification option, forward group port map 1d h 111 vpefgpm vlan priority enable and forward group port map 1e h 112 spefgpm service priority enable and forward group port map 1f h 113 ifntfgpm input force no tag and forward group port map 20 h 114 iffgpm ingress filter andforward group port map 21 h 115 vsdfgpm vlan security disable and forward group port map 22 h 116 bt0 buffer threshold register 0 23 h 118 bt1 buffer threshold register 1 24 h 118 imeijt igmp/mldtrap enable and input jam threshold register 25 h 118 q2wvecpo queue 2 weight, vid exist check, and pppoe port only 26 h 119 q3wbpvao queue 3 weight, back to port vlan, and admit only vlan-tagged 27 h 119 idtep input double tag enable, and p0vid[11:4] 28 h 120 odtep output double tag enable, and p1vid[11:4] 29 h 120 otbp output tag bypass, and p2vid[11:4] 2a h 121 p11_4 p3vid[11:4], and p4vid[11:4] 2b h 121 racp reserved address control, and p5vid[11:4] 2c h 122 phyc phy control register 2d h 122 atet adm tag ether type 2e h 123 pr phy restart register 2f h 123 misc miscellaneous register 30 h 124 bbc0 basic bandwidth control register 0 31 h 125 bbc1 basic bandwidth control register 1 32 h 125 bce bandwidth control enable register 33 h 126 ebc0 extended bandwidth control register 0 34 h 128 table 51 registers overview (cont?d) register short name register long name offset address page number
data sheet 83 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description ebc1 extended bandwidth control register 1 35 h 129 ebc2 extended bandwidth control register 2 36 h 129 ebc3 extended bandwidth control register 3 37 h 130 ebc4 extended bandwidth control register 4 38 h 130 ebc5 extended bandwidth control register 5 39 h 131 dvmebc6 default vlan member and extended bandwidth control register 6 3a h 131 ns0 new storm register 0 3b h 132 ns1 new storm register 1 3c h 133 nrac0 new reserve address control register 0 3d h 133 nrac1 new reserve address control register 1 3e h 135 hic hardware igmp control register 3f h 136 vf0l vlan filter 0 low 40 h 137 vf0h vlan filter 0 high 41 h 138 vf1l vlan filter 1 low 42 h vf1h vlan filter 1 high 43 h vf2l vlan filter 2 low 44 h vf2h vlan filter 2 high 45 h vf3l vlan filter 3low 46 h vf3h vlan filter 3 high 47 h vf4l vlan filter 4 low 48 h vf4h vlan filter 4 high 49 h vf5l vlan filter 5 low 4a h vf5h vlan filter 5 high 4b h vf6l vlan filter 6 low 4c h vf6h vlan filter 6 high 4d h vf7l vlan filter 7 low 4e h vf7h vlan filter 7 high 4f h vf8l vlan filter 8 low 50 h vf8h vlan filter 8 high 51 h vf9l vlan filter 9 low 52 h vf9h vlan filter 9 high 53 h vf10l vlan filter 10 low 54 h vf10h vlan filter 10 high 55 h vf11l vlan filter 11 low 56 h vf11h vlan filter 11 high 57 h vf12l vlan filter 12 low 58 h vf12h vlan filter 12 high 59 h vf13l vlan filter 13 low 5a h vf13h vlan filter 13 high 5b h vf14l vlan filter 14 low 5c h table 51 registers overview (cont?d) register short name register long name offset address page number
samurai-6m/mx adm6996m/mx registers description data sheet 84 rev. 1.31, 2005-11-25 vf14h vlan filter 14 high 5d h vf15l vlan filter 15 low 5e h vf15h vlan filter 15 high 5f h tf0 type filter 0 60 h 139 tf1 type filter 1 61 h tf2 type filter 2 62 h tf3 type filter 3 63 h tf4 type filter 4 64 h tf5 type filter 5 65 h tf6 type filter 6 66 h tf7 type filter 7 67 h pf_1_0 protocol filter 1 and 0 68 h 140 pf_3_2 protocol filter 3 and 2 69 h pf_5_4 protocol filter 5 and 4 6a h pf_7_6 protocol filter 7 and 6 6b h spm0 service priority mapping 0 6c h 140 spm1 service priority mapping 1 6d h 141 spm2 service priority mapping 2 6e h 142 spm3 service priority mapping 3 6f h 143 spm4 service priority mapping 4 70 h 144 spm5 service priority mapping 5 71 h 145 spm6 service priority mapping 6 72 h 145 spm7 service priority mapping 7 73 h 146 ra_01_00 reserve action for 0180c2000001~0180c2000000 74 h 147 ra_03_02 reserve action for 0180c2000003~0180c2000002 75 h ra_05_04 reserve action for 0180c2000005~0180c2000004 76 h ra_07_06 reserve action for 0180c2000007~0180c2000006 77 h ra_09_08 reserve action for 0180c2000009~0180c2000008 78 h ra_0b_0a reserve action for 0180c200000b~0180c200000a 79 h ra_0d_0c reserve action for 0180c200000d~0180c200000c 7a h ra_0f_0e reserve action for 0180c200000f~0180c200000e 7b h ra_11_10 reserve action for 0180c2000011~0180c2000010 7c h table 51 registers overview (cont?d) register short name register long name offset address page number
data sheet 85 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description ra_13_12 reserve action for 0180c2000013~0180c2000012 7d h ra_15_14 reserve action for 0180c2000015~0180c2000014 7e h ra_17_16 reserve action for 0180c2000017~0180c2000016 7f h ra_19_18 reserve action for 0180c2000019~0180c2000018 80 h ra_1b_1a reserve action for 0180c200001b~0180c200001a 81 h ra_1d_1c reserve action for 0180c200001d~0180c200001c 82 h ra_1f_1e reserve action for 0180c200001f~0180c200001e 83 h ra_21_20 reserve action for 0180c2000021~0180c2000020 84 h ra_23_22 reserve action for 0180c2000023~0180c2000022 85 h ra_25_24 reserve action for 0180c2000025~0180c2000024 86 h ra_27_26 reserve action for 0180c2000027~0180c2000026 87 h ra_29_28 reserve action for 0180c2000029~0180c2000028 88 h ra_2b_2a reserve action for 0180c200002b~0180c200002a 89 h ra_2d_2c reserve action for 0180c200002d~0180c200002c 8a h ra_2f_2e reserve action for 0180c200002f~0180c200002e 8b h tuf0 tcp/udp filter 0 8c h 150 tuf1 tcp/udp filter 1 8d h tuf2 tcp/udp filter 2 8e h tuf3 tcp/udp filter 3 8f h tuf4 tcp/udp filter 4 90 h tuf5 tcp/udp filter 5 91 h tuf6 tcp/udp filter 6 92 h tuf7 tcp/udp filter 7 93 h tfa type filter action 94 h 150 pfa protocol filter action 95 h 151 tua0 tcp/udp action 0 96 h 152 tua1 tcp/udp action 1 97 h 153 tua2 tcp/udp action 2 98 h 154 table 51 registers overview (cont?d) register short name register long name offset address page number
samurai-6m/mx adm6996m/mx registers description data sheet 86 rev. 1.31, 2005-11-25 eicstic extended igmp control/special tag insert control 99 h 155 ie interrupt enable register 9a h 156 is interrupt status register 9b h 157 sc security control register 9c h 157 ci0 chip identifier 0 a0 h 158 ci1 chip identifier 1 a1 h 158 ps0 port status 0 a2 h 158 ps1 port status 1 a3 h 159 ps2 port status 2 a4 h 160 ps3 port status 3 a5 h 161 cb0 cable broken 0 a6 h 161 cb1 cable broken 1 a7 h 162 cl0 port 0 receive packet counter low a8 h 162 ch0 port 0 receive packet counter high a9 h 163 cl1 port 1 receive packet counter low ac h ch1 port 1 receive packet counter high ad h cl2 port 2 receive packet counter low b0 h ch2 port 2 receive packet counter high b1 h cl3 port 3 receive packet counter low b4 h ch3 port 3 receive packet counter high b5 h cl4 port 4 receive packet counter low b6 h ch4 port 4 receive packet counter high b7 h cl5 port 5 receive packet counter low b8 h ch5 port 5 receive packet counter high b9 h cl6 port 0 receive packet byte count low ba h ch6 port 0 receive packet byte count high bb h cl7 port 1 receive packet byte count low be h ch7 port 1 receive packet byte count high bf h cl8 port 2 receive packet byte count low c2 h ch8 port 2 receive packet byte count high c3 h cl9 port 3 receive packet byte count low c6 h ch9 port 3 receive packet byte count high c7 h cl10 port 4 receive packet byte count low c8 h ch10 port 4 receive packet byte count high c9 h cl11 port 5 receive packet byte count low ca h ch11 port 5 receive packet byte count high cb h cl12 port 0 transmit packet count low cc h ch12 port 0 transmit packet count high cd h cl13 port 1 transmit packet count low d0 h ch13 port 1 transmit packet count high d1 h cl14 port 2 transmit packet count low d4 h table 51 registers overview (cont?d) register short name register long name offset address page number
data sheet 87 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description ch14 port 2 transmit packet count high d5 h cl15 port 3 transmit packet count low d8 h ch15 port 3 transmit packet count high d9 h cl16 port 4 transmit packet count low da h ch16 port 4 transmit packet count high db h cl17 port 5 transmit packet count low dc h ch17 port 5 transmit packet count high dd h cl18 port 0 transmit packet byte count low de h ch18 port 0 transmit packet byte count high df h cl19 port 1 transmit packet byte count low e2 h ch19 port 1 transmit packet byte count high e3 h cl20 port 2 transmit packet byte count low e6 h ch20 port 2 transmit packet byte count high e7 h cl21 port 3 transmit packet byte count low ea h ch21 port 3 transmit packet byte count high eb h cl22 port 4 transmit packet byte count low ec h ch22 port 4 transmit packet byte count high ed h cl23 port 5 transmit packet byte count low ee h ch23 port 5 transmit packet byte count high ef h cl24 port 0 collision count low f0 h ch24 port 0 collision count high f1 h cl25 port 1 collision count low f4 h ch25 port 1 collision count high f5 h cl26 port 2 collision count low f8 h ch26 port 2 collision count high f9 h cl27 port 3 collision count low fc h ch27 port 3 collision count high fd h cl28 port 4 collision count low fe h ch28 port 4 collision count high ff h cl29 port 5 collision count low 100 h ch29 port 5 collision count high 101 h cl30 port 0 error count low 102 h ch30 port 0 error count high 103 h cl31 port 1 error count low 106 h ch31 port 1 error count high 107 h cl32 port 2 error count low 10a h ch32 port 2 error count high 10b h cl33 port 3 error count low 10e h ch33 port 3 error count high 10f h cl34 port 4 error count low 110 h ch34 port 4 error count high 111 h table 51 registers overview (cont?d) register short name register long name offset address page number
samurai-6m/mx adm6996m/mx registers description data sheet 88 rev. 1.31, 2005-11-25 cl35 port 5 error count low 112 h ch35 port 5 error count high 113 h off0 over-flow flag 0 114 h 165 off1 over-flow flag 1 115 h 166 off2 over-flow flag 2 116 h 166 off3 over-flow flag 3 117 h 167 off4 over-flow flag 4 118 h 168 off5 over-flow flag 5 119 h 169 hsl hardware setting low register 130 h 169 hsh hardware setting high register 131 h 170 aa1 assign address [15:0] register 132 h 171 aa2 assign address [31:16] register 133 h 171 aa3 assign address [47:32] register 134 h 172 ao assign option register 135 h 172 mirr0 mirror register 0 136 h 173 mirr1 mirror register 1 137 h 174 svp security violation port 138 h 175 ss0 security status 0 139 h 175 ss1 security status 1 13a h 176 flas first lock address search 13b h 176 fla1 first lock address [15:0] 13c h 177 fla2 first lock address [31:16] 13d h 177 fla3 first lock address [47:32] 13e h 177 flf first lock fid 13f h 178 ccl counter control low register 140 h 178 cch counter control high register 141 h 179 csl counter status low register 142 h 179 csh counter status high register 143 h 179 phy_c0 phy control register of port 0 200 h 180 phy_s0 phy status register of port 0 201 h 182 phy_i0_a phy identifier register of port 0 (a) 202 h 183 phy_i0_b phy identifier register of port 0 (b) 203 h 184 anap0 auto negotiation advertisement register of port 0 204 h 185 anlpa0 auto negotiation link partner ability register of port 0 205 h 186 ane0 auto negotiation expansion register of port 0 206 h 187 npt0 next page transmit register of port 0 207 h 188 lpnp0 link partner next page register of port 0 208 h 189 phy_c1 phy control register of port 1 220 h phy_s1 phy status register of port 1 221 h phy_i1_a phy identifier register of port 1 (a) 222 h table 51 registers overview (cont?d) register short name register long name offset address page number
data sheet 89 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description the register is addressed wordwise. phy_i1_b phy identifier register of port 1 (b) 223 h anap1 auto negotiation advertisement register of port 1 224 h anlpa1 auto negotiation link partner ability register of port 1 225 h ane1 auto negotiation expansion register of port 1 226 h npt1 next page transmit register of port 1 227 h lpnp1 link partner next page register of port 1 228 h phy_c2 phy control register of port 2 240 h phy_s2 phy status register of port 2 241 h phy_i2_a phy identifier register of port 2 (a) 242 h phy_i2_b phy identifier register of port 2 (b) 243 h anap2 auto negotiation advertisement register of port 2 244 h anlpa2 auto negotiation link partner ability register of port 2 245 h ane2 auto negotiation expansion register of port 2 246 h npt2 next page transmit register of port 2 247 h lpnp2 link partner next page register of port 2 248 h phy_c3 phy control register of port 3 260 h phy_s3 phy status register of port 3 261 h phy_i3_a phy identifier register of port 3 (a) 262 h phy_i3_b phy identifier register of port 3 (b) 263 h anap3 auto negotiation advertisement register of port 3 264 h anlpa3 auto negotiation link partner ability register of port 3 265 h ane3 auto negotiation expansion register of port 3 266 h npt3 next page transmit register of port 3 267 h lpnp3 link partner next page register of port 3 268 h phy_c4 phy control register of port 4 280 h phy_s4 phy status register of port 4 281 h phy_i4_a phy identifier register of port 4 (a) 282 h phy_i4_b phy identifier register of port 4 (b) 283 h anap4 auto negotiation advertisement register of port 4 284 h anlpa4 auto negotiation link partner ability register of port 4 285 h ane4 auto negotiation expansion register of port 4 286 h npt4 next page transmit register of port 4 287 h lpnp4 link partner next page register of port 4 288 h table 51 registers overview (cont?d) register short name register long name offset address page number
samurai-6m/mx adm6996m/mx registers description data sheet 90 rev. 1.31, 2005-11-25 table 52 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is readable and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latches high signal at high level, cleared on read sw can read the register latch low, self clearing llsc latches high signal at low-level, cleared on read sw can read the register latch high, mask clearing lhmk latches high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latches high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiates the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiates the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiates the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiates the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interrupt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is readable and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be cleared due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is readable and writable by sw. table 53 registers clock domains clock short name description ??
data sheet 91 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description 4.1 eeprom basic registers signature register p0 basic control register sig offset reset value signature register 00 h 4154 h field bits type description sig 15:0 ro signature the value must be 4154 h . samurai-6m/6mx (adm6996m/mx) uses this value to check if eeprom is attached. if the value in the eeprom is not equal to 4154 h , samurai-6m/6mx (adm6996m/mx) will stop loading the eeprom even if eeprom is attached and samurai-6m/6mx (adm6996m/mx) will use the default value inside the chip to initialize. p0bc offset reset value p0 basic control register 01 h 040f h ur 6,* uz &526 6b(( uz 6(/) ;b(( uz 39,'b uz 33 uz 33( uz ,39/ $1 uz 3' uz 237( uz '$ uz 6$ uz $1( uz )&(
samurai-6m/mx adm6996m/mx registers description data sheet 92 rev. 1.31, 2005-11-25 field bits type description cross_ee 15 rw crossover auto detect enable this bit is used together with the value (cross_hw) on the pin eesk / sdc during the power on reset and the value (wait_init) on the pin wait_init during the normal mode to decide if phy enables this function. this bit is useless in port 5. combine with wait_initand cross_hw, the crossover auto detect capability is summarized as below : {wait_init, cross_hw, cross_ee} description 1x1 b , this port will enable crossover auto detect enable function 1x0 b , this port will disable crossover auto detect enable function 01x b , this port will enable crossover auto detect enable function 000 b , this port will disable crossover auto detect enable function 001 b , this port will enable crossover auto detect enable function selfx_ee 14 rw select fx this bit is used together with the value (p4fx_hw) on the pin p4fx during the power on reset to decide if the phy operates on the fiber mode. this bit is useless in port 5. port 0, 1, 2, 3: follow selfx_ee description and port 4: follow {p4fx_hw, selfx_ee} description 1x b , port 4: port 4 will operate in the fiber mode 00 b , port 4: port 4 will operate in the twisted mode 01 b , port 4: port 4 will operate in the fiber mode pvid3_0 13:10 rw private vid see 0028 h ~ 002c h to find the other pvid [11:4] pp 9:8 rw port priority 00 b , assign packets to queue 0 01 b , assign packets to queue 1 10 b , assign packets to queue 2 11 b , assign packets to queue 3 ppe 7 rw port priority enable 0 b , the port priority is disabled 1 b , the port priority is enabled ipvlan 6 rw ip over vlan pri 0 b , use the priority bits in the tag header to assign the priority queue 1 b , use the ip pri to assign the priority queue pd 5 rw port disable 0 b , port 0, 1, 2, 3, 4: phy works normally. port 5: port 5 works normally 1 b , port 0, 1, 2, 3, 4. phy is disabled. port 5: port 5 is forced to link down opte 4 rw output packet tagging enable 0 b , untagged packets are transmitted 1 b , tagged packets are transmitted da 3 rw duplex ability it is useless in port 5. 0 b , recommend phy to work in the half duplex mode 1 b , recommend phy to work in the full duplex mode
data sheet 93 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers p0 extended control register sa 2 rw speed ability 0 b , recommend phy to work in the 10m mode 1 b , recommend phy to work in the 100m mode ane 1 rw auto negotiation enable 0 b , recommend phy to work without auto negotiation 1 b , recommend phy to work with auto negotiation, when the value on the pin dupcol0 during the power on reset is 1 fce 0 rw flow control enable 0 b , recommend mac to work without pause or back pressure 1 b , in full duplex, recommend mac to work with pause when the value on the txd0 during the power on reset is 1. in half duplex, recommend mac to work with back pressure when the value on the dupcol2 during the power on reset is 1 table 54 p1~p5 basic control registers register short name register long name offset address page number p1bc p1 basic control register 03 h p2bc p2 basic control register 05 h p3bc p3 basic control register 07 h p4bc p4 basic control register 08 h p5bc p5 basic control register 09 h p0ec offset reset value p0 extended control register 02 h 0000 h field bits type description res 15 r reserved ad135 14 rw aging disable p1, p3, and p5. 0 b , aging function is enabled 1 b , aging function is disabled ld135 13 rw learning disable p1, p3, and p5. 0 b , learning function is enabled 1 b , learning function is disabled field bits type description u 5hv uz $' uz /' uz 01$ u 5hv uz $' uz /' uz 01$
samurai-6m/mx adm6996m/mx registers description data sheet 94 rev. 1.31, 2005-11-25 similar registers system control register 0 mna135 12:8 rw maximum number of addresses learned from the port (p1, p3, and p5). note: set value to others = limit the number of addresses to be learned. 00000 b , doesn?t limit the number of addresses to be learned res 7 r reserved ad024 6 rw aging disable p0, p2, and p4. 0 b , aging function is enabled. 1 b , aging function is disabled. ld024 5 rw learning disable p0, p2, and p4. 0 b , learning function is enabled. 1 b , learning function is disabled. mna024 4:0 rw maximum number of addresses learned from the port (p0, p2, and p4). note: set value to others = limit the number of addresses to be learned. 00000 b , doesn?t limit the number of addresses to be learned table 55 px_ec registers register short name register long name offset address page number p1ec p1 extended control register 02 h p2ec p2 extended control register 04 h p3ec p3 extended control register 04 h p4ec p4 extended control register 06 h p5ec p5 extended control register 06 h sc0 offset reset value system control register 0 0a h 5902 h field bits type description ercmpth 15:12 rw earlier cycles for transmission it means the earlier cycles for transmission used in samurai-6m/6mx (adm6996m/mx). it is for the engineer debug purpose. field bits type description uz (5&037+ uz 3&5 uz 3&( uz 59,' uz 59,' uz 59,' ))) uz '),' uz 177( uz 78 uz 30
data sheet 95 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description system control register 1 pcr 11 rw priority change rule 0 b , use vlan_pri field in the matched vlan filter 1 b , reverse pri in the same way as untagged packet pce 10 rw priority change enable 0 b , do not change the priority in the tag header 1 b , change the priority field in the tag header rvid0 9 rw replace vid0 0 b , do not replace 1 b , replace rvid1 8 rw replace vid1 0 b , do not replace 1 b , replace rvidfff 7 rw replace vidfff 0 b , do not replace 1 b , replace dfid 6:3 rw default fid see chapter 3.1.14.7 fid and vlan boundary for more detailed information. ntte 2 rw new transmit tag enable 0 b , use old 1 b , use new tu 1 rw tos using 0 b , use the most significant 6 bits of the tos field in the ipv4 header to map the priority queue 1 b , use the most significant 3 bits of the tos field in the ipv4 header to map the priority queue pm 0 rw pppoe manage when the port is configured as pppoe only, the port will only transmit the pppoe packets. but when the packet is a management one, users could configure pppoe manage to 1 b to transmit this packet on the pppoe only port even if it is not a pppoe packet. samurai-6m/6mx (adm6996m/mx) identifies packets with ether-type = 8863 h or 8864 h as the pppoe packet. sc1 offset reset value system control register 1 0b h 8001 h field bits type description uz ')() ' uz ,) uz $6& uz 6,& uz 6,0 uz 6,$ uz &06 uz 7( uz 76,( uz &3'& uz 6925 uz 692$ uz 6926 uz 692' uz 1(
samurai-6m/mx adm6996m/mx registers description data sheet 96 rev. 1.31, 2005-11-25 field bits type description dfefd 15 rw disable far-end-fault detection 0 b , far-end-fault detect ion is enabled 1 b , far-end-fault detect ion is disabled if 14 rw input filter 0 b , discardes packets directly when storming or the lack of input buffers 1 b , forwardes packets to the un-congested port when storming or the lack of input buffers asc 13:12 rw additional snooping control these bits are used when the packets on the incoming port with the ethernet destination address = 01005exxxxxx h /3333xxxxxx h are not igmp_ip/ mld_ipv/mld_ipv6 packets and not found in the learning table or the hardware igmp table. 00 b , as normal multicast packets 01 b , dropped 10 b , send to cpu if the receiving port is non-cpu port or send to multicast portmap if the receiving is the cpu port 11 b , reserved sic 11 rw source intrusion condition 0 b , learning table source violation does not consider the port match 1 b , learning table source violation takes the port match into consideration sim 10 rw source intrusion must 0 b , learning table source violation will be effective in the following conditions. (1) the packets are not the management packets. (2) the packets are the management packets but source violation over reserve ( svor ) is 1 b 1 b , must follow the learning table source violation rules sia 9 rw source intrusion action 0 b , discarded 1 b , send to the cpu port cms 8 rw carrier mask select (reserved for test) 0 b , mask crs of 4 cycles 1 b , mask crs of 5 cycles te 7 rw port 3 and port 4 trunk enable 0 b , no trunk is enabled 1 b , port 3 and port 4 are trunked tsie 6 rw transmit short ipg enable 0 b , 96 bits time of ipg is used 1 b , 88/96 bits time of ipg is used cpdc 5 rw cpu port doesn? t check cpu port doesn? t check crc, for packets with special tag. 0 b , checks 1 b , doesn?t check
data sheet 97 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description multicast snooping register svor 4 rw source violation over reserve this bit is used when the management packet with da = 0180c20000xx h violates the source rule. 0 b , source violation doesn?t change the forwarding algorithm 1 b , source violation will change the forwarding algorithm svoa 3 rw source violation over arp/rarp this bit is used when the arp/rarp packet classified as management that violates the source rule. 0 b , source violation doesn?t change the forwarding algorithm 1 b , source violation will change the forwarding algorithm svos 2 rw source violation over snooping this bit is used when the mld_ipv6/mld_ip/igmp/ip packet classified as management that violates the source rule. 0 b , source violation doesn?t change the forwarding algorithm 1 b , source violation will change the forwarding algorithm svod 1 rw source violation over default this bit is used when the packet that is not the same as the above and it is classified as management that violates the source rule. 0 b , source violation doesn?t change the forwarding algorithm 1 b , source violation will change the forwarding algorithm ne 0 rw new eeprom 0 b , use old eeprom functions 1 b , new eeprom function is enabled ms offset reset value multicast snooping register 0c h 0000 h field bits type description scpa 15:14 rw snooping control packet action 00 b , igmp portmap is 000000 b 01 b , igmp portmap is the multicast portmap 10 b , if the incoming port is not the cpu port, then the igmp portmap is the cpu port. if the incoming port is the cpu port, then the igmp portmap is the multicast portmap except the cpu port 11 b , if the incoming port is not the cpu port, then the multicast portmap is the cpu port. if the incoming port is the cpu port, then the multicast portmap is the default output ports except the cpu port field bits type description uz 6&3$ uz 6&33 ( uz 6&33 uz 6&377+ uz 6&37 & uz 6&37 0 uz 6&37 6 uz 70, 3 uz 70,3 uz 7,3 uz +,3, uz +,6( uz +,'5 (
samurai-6m/mx adm6996m/mx registers description data sheet 98 rev. 1.31, 2005-11-25 scppe 13 rw snooping control packet priority enable 0 b , disable 1 b , enable scpp 12:11 rw snooping control packet priority 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 scptth 10:9 rw snooping control packet transmission tag handle 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged scptc 8 rw snooping control packet treated as cross_vlan packet 0 b , doesn?t identify 1 b , identifies as the cross_vlan packet scptm 7 rw snooping control packet treated as management packet 0 b , doesn?t identify 1 b , identifies as the management packet scpts 6 rw snooping control packet treated as span packet 0 b , doesn?t identify 1 b , identifies as the span packet tmi6p 5 rw trap mld_ipv6 packet 0 b , doesn?t trap 1 b , traps tmip 4 rw trap mld_ip packet 0 b , doesn?t trap 1 b , traps tip 3 rw trap igmp_ip packet 0 b , doesn?t trap 1 b , trasp hipi 2 rw hardware igmp packet ignore cpu port 0 b , igmp packet forwards to cpu also when hardware igmp snooping is enabled 1 b , igmp packet doesn?t forward to cpu when hardware igmp snooping is enabled hise 1 rw hardware igmp snooping enable 0 b , disable hardware igmp snooping 1 b , enable hardware igmp snooping hidre 0 rw hardware igmp default router enable 0 b , disable 1 b , enable field bits type description
data sheet 99 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description arp/rarp register ar offset reset value arp/rarp register 0d h 0000 h field bits type description res 15 r reserved imp 14 rw ip multicast packet treated as cross_vlan packet 0 b , doesn?t identify 1 b , identifies as the cross_vlan packet upt 13 rw unicast packet treated as cross_vlan packet 0 b , doesn?t identify 1 b , identifies as the cross_vlan packet when there is a match in the learning table rpt 12 rw r arp packet treated as cross_vlan packet 0 b , doesn?t identify 1 b , identifies as the cross_vlan packet rapa 11:10 rw rarp/arp packet action 00 b , arp/rarp portmap is 000000 b 01 b , arp/rarp portmap is the broadcast portmap 10 b , if the incoming port is not the cpu port, then the arp/rarp portmap is the cpu port. if the incoming port is the cpu port, then the arp/rarp portmap is the broadcast portmap except the cpu port 11 b , if the incoming port is not the cpu port, then the arp/rarp portmap is the cpu port. if the incoming port is the cpu port, then the arp/rarp portmap is the default output port except the cpu port rappe 9 rw rarp/arp packet priority enable 0 b , disable 1 b , enable rapp 8:7 rw rarp/arp packet priority 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 rapoth 6:5 rw rarp/arp packet output tag handle 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged u 5hv uz ,03 uz 837 uz 537 uz 5$3$ uz 5$33 ( uz 5$33 uz 5$327+ uz $37 uz 5$37 0 uz 7$37 6 uz 7$3 uz 753
samurai-6m/mx adm6996m/mx registers description data sheet 100 rev. 1.31, 2005-11-25 vlan priority map register apt 4 rw arp packet treated as cross _ vlan packet 0 b , doesn?t identify 1 b , identifies as the cross_vlan packet raptm 3 rw rarp/arp packet treated as management packet 0 b , doesn?t identify 1 b , identifies as the management packet tapts 2 rw rarp/arp packet treated as span packet 0 b , doesn?t identify 1 b , identifies as the span packet tap 1 rw trap arp packet 0 b , doesn?t trap 1 b , traps trp 0 rw trap rarp packet 0 b , doesn?t trap 1 b , traps vpm offset reset value vlan priority map register 0e h fa50 h field bits type description pq7 15:14 rw priority queue 7 these 2 bits are used as the priority queue when the tagged packets with the user priority = 111 b are received on the port. 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 pq6 13:12 rw priority queue 6 these 2 bits are used as the priority queue when the tagged packets with the user priority = 110 b are received on the port. pq5 11:10 rw priority queue 5 these 2 bits are used as the priority queue when the tagged packets with the user priority = 101 b are received on the port. pq4 9:8 rw priority queue 4 these 2 bits are used as the priority queue when the tagged packets with the user priority = 100 b are received on the port. field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
data sheet 101 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description tos priority map register pq3 7:6 rw priority queue 3 these 2 bits are used as the priority queue when the tagged packets with the user priority = 011 b are received on the port. pq2 5:4 rw priority queue 2 these 2 bits are used as the priority queue when the tagged packets with the user priority = 010 b are received on the port. pq1 3:2 rw priority queue 1 these 2 bits are used as the priority queue when the tagged packets with the user priority = 001 b are received on the port. pq0 1:0 rw priority queue 0 these 2 bits are used as the priority queue when the tagged packets with the user priority = 000 b are received on the port. tpm offset reset value tos priority map register 0f h fa50 h field bits type description pq7 15:14 rw priority queue 7 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 111 b 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 pq6 13:12 rw priority queue 6 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 110 b pq5 11:10 rw priority queue 5 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 101 b pq4 9:8 rw priority queue 4 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 100 b pq3 7:6 rw priority queue 3 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 011 b field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
samurai-6m/mx adm6996m/mx registers description data sheet 102 rev. 1.31, 2005-11-25 system control register 2 pq2 5:4 rw priority queue 2 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 010 b pq1 3:2 rw priority queue 1 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 001 b pq0 1:0 rw priority queue 0 these 2 bits are used as the priority queue, when the most significant 3 bits in the tos field are 000 b sc2 offset reset value system control register 2 10 h 0040 h field bits type description dm_q3 15:14 rw discard mode q3 discard mode (drop scheme for packets classified as q3) . see chapter 3.1.11 smart discard for more detail information. dm_q2 13:12 rw discard mode q2 discard mode (drop scheme for packets classified as q2) . see chapter 3.1.11 smart discard for more detail information. dm_q1 11:10 rw discard mode q1 discard mode (drop scheme for packets classified as q1) . see chapter 3.1.11 smart discard for more detail information. dm_q0 9:8 rw discard mode q0 discard mode (drop scheme for packets classified as q0) . see chapter 3.1.11 smart discard for more detail information. ad 7 rw aging disable useless in samurai-6m/6mx (adm6996m/mx) 0 b , age enabled 1 b , age disabled cc 6 rw rx clock change to tx clock for gpsi interface 0 b , samurai-6m/6mx (adm6996m/mx) does not use tx clock to replace rx clock when rx clock stops. 1 b , samurai-6m/6mx (adm6996m/mx) uses tx clock to replace rx clock when rx clock stops field bits type description uz '0b4 uz '0b4 uz '0b4 uz '0b4 uz $' uz && uz 03 uz &&' uz %' uz 6( uz 67
data sheet 103 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description system control register 3 mp 5 rw multicast packet counted into the storm counter 0 b , only broadcast packets are counted into the storming counter 1 b , multicast and broadcast packets are counted into the storming counter ccd 4 rw crc check disable 0 b , checks crc 1 b , doesn?t check crc bd 3 rw back off disable 0 b , back-off is enabled 1 b , back-off is disabled se 2 rw storming enable it is used in adm6996l/f style storm control. 0 b , disable broadcast/multicast storm protection. 1 b , enable boradcast/multicast storm protection. st 1:0 rw storming threshold[1:0] it is used in adm6996l/f style storm control. sc3 offset reset value system control register 3 11 h e300 h field bits type description cpn 15:13 rw cpu port number 000 b , the cpu is attached to port 0 001 b , the cpu is attached to port 1 010 b , the cpu is attached to port 2 011 b , the cpu is attached to port 3 100 b , the cpu is attached to port 4 101 b , the cpu is attached to port 5 111 b , no cpu exists stre 12 rw special tag receive enable 0 b , samurai-6m/6mx (adm6996m/mx) doesn?t identify the special tag for the incoming packets 1 b , samurai-6m/6mx (adm6996m/mx) identifies the special tag for the incoming packets field bits type description uz &31 uz 675( uz 677( uz 3 uz 03/ uz 16( uz 7%9 uz 0&( uz 42 uz ,3, uz $76
samurai-6m/mx adm6996m/mx registers description data sheet 104 rev. 1.31, 2005-11-25 system control register 4 stte 11 rw special tag transmit enable 0 b , samurai-6m/6mx (adm6996m/mx) does not insert special tag for the packets transmitted to the cpu port 1 b , samurai-6m/6mx (adm6996m/mx) inserts special tag for the packets transmitted to the cpu port. p10rw pause also adds special tag when special tag transmit is enabled . 0 b , does not add special tag on the pause packets 1 b , adds special tag in the pause packets mpl 9:7 rw max packet length 000 b , 1518 bytes 001 b , 1536 bytes 010 b , 1664 bytes 110 b , 1522 bytes x11 b , 1784 bytes 10x b , 1784 bytes nse 6 rw new storming enable 0 b , uses the adm6996l/f style storming control 1 b , uses the samurai-6m/6mx (adm6996m/mx) style storming control tbv 5 rw tag base vlan 0 b , port vlan 1 b , tagged vlan mce 4 rw mac clone enable 0 b , mac clone is disabled 1 b , mac clone is enabled qo 3 rw queue option it? s the test for the designer in the queue control. ipi 2 rw interrupt polarity inverter 0 b , the interrupt signal is active pull low 1 b , the interrupt signal is active pull high ats 1:0 rw aging timer select 00 b , 300 seconds 01 b , 75 seconds 10 b , 18 seconds 11 b , 1 second sc4 offset reset value system control register 4 12 h 3600 h field bits type description
data sheet 105 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description field bits type description dp 15 rw drop packet when excessive collision happen 0 b , doesn?t drop 1 b , drops dup_col_se p 14 rw duplex and col separate 0 b , indicates the duplex and collision status at the same time 1 b , indicates the duplex status only res 13:12 rw reserved tle 11 rw ten limit enable this function works only when full flow control/half back pressure is enabled. 0 b , the switch will not ignore 10 mbit/s paths even when the ten limit reaches 1 b , the switch will forward packets with multicast, broadcast, or unicast but not learned da addresses from 100 mbit/s only to 100 mbit/s ports and ignore the 10m paths when the ten limit reaches. this function allows the switch to balance the high and the low speed res 10 rw reserved res 9 rw reserved o5fl 8 rw old p5 first lock 0 b , first lock is disabled 1 b , first lock is enabled o4fl 7 rw old p4 first lock 0 b , first lock is disabled 1 b , first lock is enabled o3fl 6 rw old p3 first lock 0 b , first lock is disabled 1 b , first lock is enabled pi 5 rw pause ignore 0 b , doesn?t ignore pause packets 1 b , ignores pause packets in half duplex or in full duplex when flow control is not enabled o2fl 4 rw old p2 first lock 0 b , first lock is disabled 1 b , first lock is enabled dual- color-ee 3rw dual color in mdc / mdio with cpu see chapter 3.1.12 led display for more detailed information. 0 b , single color 1 b , dual color uz '3 uz '83b &2/ uz 5hv uz 7/( uz 5hv uz 5hv uz 2)/ uz 2)/ uz 2)/ uz 3, uz 2)/ uz '8$/ uz 2)/ uz /(' uz 2)/
samurai-6m/mx adm6996m/mx registers description data sheet 106 rev. 1.31, 2005-11-25 port 0 security option port spanning tree state and forward group port map. o1fl 2 rw old p1 first lock 0 b , first lock is disabled 1 b , first lock is enabled led-enable 1 rw led enable 0 b , disable 1 b , enable o0fl 0 rw old p0 first lock 0 b , first lock is disabled 1 b , first lock is enabled p0so offset reset value port 0 security option 13 h 01d5 h field bits type description res 15 r reserved cp 14 rw close port 0 b , doesn?t close the port 1 b , when port security exists, the port is closed automatically pso 13:11 rw port security option 001 b , unknown to cpu 010 b , discard unknown 011 b , first lock 100 b , first link lock 101 b , assign lock 110 b , assign link lock stps 10:9 rw spanning tree port status the samurai-6m/6mx (adm6996m/mx) supports 4 port status to support spanning tree protocol . 00 b , forwarding state. the port acts as the normal mode 01 b , disabled state . the port entity will not transmit and receive any packets. learning is disabled in this state 10 b , learning state . the port entity will only transmit and receive span packets. all other packets are discarded. learning is enabled for all good frames 11 b , blocking/listening. only the span packets defined by samurai- 6m/6mx (adm6996m/mx) will be received and transmitted. all other packets are discarded by the port entity. learning is disabled in this state field bits type description u 5hv uz &3 uz 362 uz 6736 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 107 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers unicast port map and forward group port map p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member table 56 pxso registers register short name register long name offset address page number p1so port 1 security option 14 h p2so port 2 security option 15 h p3so port 3 security option 16 h p4so port 4 security option 17 h p5so port 5 security option 18 h ufgpm offset reset value unicast port map andforward group port map 19 h ffd5 h field bits type description u 5hv uz 83 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai-6m/mx adm6996m/mx registers description data sheet 108 rev. 1.31, 2005-11-25 broadcast port map andforward group port map field bits type description res 15 r reserved up 14:9 rw unicast portmap see chapter 3.1.20 packet forwarding for more detailed information. p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member bfgpm offset reset value broadcast port map andforward group port map 1a h ffd5 h field bits type description res 15 r reserved bp 14:9 rw broadcast portmap see chapter 3.1.20 packet forwarding for more detailed information. u 5hv uz %3 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 109 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description multicast port map and forward group port map p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member mfgpm offset reset value multicast port map and forward group port map 1b h ffd5 h field bits type description res 15 r reserved mp 14:9 rw multicast portmap see chapter 3.1.20 packet forwarding for more detailed information. p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member field bits type description u 5hv uz 03 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai-6m/mx adm6996m/mx registers description data sheet 110 rev. 1.31, 2005-11-25 reserve port map and forward group port map p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member rfgpm offset reset value reserve port map and forward group port map 1c h ffd5 h field bits type description res 15 r reserved rp 14:9 rw reserve portmap see chapter 3.1.20 packet forwarding for more detailed information. p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved field bits type description u 5hv uz 53 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 111 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description packet identification option, forward group port map p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member piofgpm offset reset value packet identification option, forward group port map 1d h ffd5 h field bits type description msph 15 rw mld snooping protocol header 0 b , protocol header is 01 h . 1 b , protocol header is 3a h . divs 14 rw do not identify vlan after snap 0 b , identify 1 b , don?t identify dii6p 13 rw do not identify ipv6 in pppoe 0 b , identify 1 b , don?t identify diips 12 rw do not identify ip in pppoe after snap 0 b , identify 1 b , don?t identify die 11 rw do not identify ether-type = 0x0800, ip ver = 6 as ipv6 packets 0 b , identify 1 b , don?t identify diip 10 rw do not identify ip in pppoe 0 b , identify 1 b , don?t identify field bits type description uz 063+ uz ',96 uz ',, 3 uz ',,3 6 uz ',( uz ',,3 uz ',6 uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai-6m/mx adm6996m/mx registers description data sheet 112 rev. 1.31, 2005-11-25 vlan priority enable and forward group port map dis 9 rw do not identify snap 0 b , identify 1 b , don?t identify p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member vpefgpm offset reset value vlan priority enable and forward group port map 1e h ffd5 h field bits type description res 15 r reserved vpe 14:9 rw vlan priority enable 0 b , do not care the pri in the tag header 1 b , pri in the tag header will be taken into priority determination consideration field bits type description u 5hv uz 93( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 113 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description service priority enable and forward group port map p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a membe res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member spefgpm offset reset value service priority enable and forward group port map 1f h ffd5 h field bits type description res 15 r reserved spe 14:9 rw service priority enable 0 b , don?t care ipv4 tos /ipv6 traffic class 1 b , care ipv4 tos/ipv6 traffic for priority decision p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member field bits type description u 5hv uz 63( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai-6m/mx adm6996m/mx registers description data sheet 114 rev. 1.31, 2005-11-25 input force no tag and forward group port map p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member ifntfgpm offset reset value input force no tag and forward group port map 20 h ffd5 h field bits type description res 15 r reserved ifnte 14:9 rw input force no tag enable 0 b , disabled 1 b , enabled p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved field bits type description u 5hv uz ,)17( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 115 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description ingress filter andforward group port map p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member iffgpm offset reset value ingress filter andforward group port map 21 h ffd5 h field bits type description res 15 r reserved ife 14:9 rw ingress filter enable 0 b , doesn?t filter 1 b , filters p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved field bits type description u 5hv uz ,)( uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
samurai-6m/mx adm6996m/mx registers description data sheet 116 rev. 1.31, 2005-11-25 vlan security disable and forward group port map p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member vsdfgpm offset reset value vlan security disable and forward group port map 22 h ffd5 h field bits type description res 15 r reserved vsd 14:9 rw vlan security disable 0 b , do not disable 1 b , disable p5 8 rw port 5 is a member of the forwarding group 0 b , port 5 is not a member 1 b , port 5 is a member p4 7 rw port 4 is a member of the forwarding group 0 b , port 4 is not a member 1 b , port 4 is a member p3 6 rw port 3 is a member of the forwarding group 0 b , port 3 is not a member 1 b , port 3 is a member res 5 r reserved p2 4 rw port 2 is a member of the forwarding group 0 b , port 2 is not a member 1 b , port 2 is a member res 3 r reserved p1 2 rw port 1 is a member of the forwarding group 0 b , port 1 is not a member 1 b , port 1 is a member res 1 r reserved field bits type description u 5hv uz 96' uz 3 uz 3 uz 3 u 5hv uz 3 u 5hv uz 3 u 5hv uz 3
data sheet 117 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description p0 0 rw port 0 is a member of the forwarding group 0 b , port 0 is not a member 1 b , port 0 is a member field bits type description
samurai-6m/mx adm6996m/mx registers description data sheet 118 rev. 1.31, 2005-11-25 buffer threshold register 0 buffer threshold register 1 igmp/mldtrap enable and input jam threshold register bt0 offset reset value buffer threshold register 0 23 h 0000 h field bits type description res 15:0 r reserved bt1 offset reset value buffer threshold register 1 24 h 0000 h field bits type description res 15:0 r reserved imeijt offset reset value igmp/mldtrap enable and input jam threshold register 25 h 1000 h u 5hv u 5hv uz 4: uz ,07( uz ,-7
data sheet 119 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description queue 2 weight, vid exist check, and pppoe port only queue 3 weight, back to port vlan, and admit only vlan-tagged field bits type description q1w 15:12 rw queue 1 weight see chapter 3.1.15 priority queue for more detail information. imte 11:6 rw igmp/mld trap enable it is a per port function. 0 b , the port does not enable its multicast snooping function. trap mld_ipv6, mld_ip and igmp_ip are useless in this port 1 b , the port enables its multicast snooping function. trap mld_ipv6, mld_ip and igmp_ip are useful in this port ijt 5:0 rw input jam threshold q2wvecpo offset reset value queue 2 weight, vid exist check, and pppoe port only 26 h 1000 h field bits type description q2w 15:12 rw queue 2 weight see chapter 3.1.15 priority queue for more detail information. vc 11:6 rw vid check it is a per port function. 0 b , doesn?t check 1 b , checks ppo 5:0 rw pppoe port only it?s a per port function 0 b , the port is not a pppoe only port 1 b , the port is a pppoe only port q3wbpvao offset reset value queue 3 weight, back to port vlan, and admit only vlan-tagged 27 h 1000 h uz 4: uz 9& uz 332
samurai-6m/mx adm6996m/mx registers description data sheet 120 rev. 1.31, 2005-11-25 input double tag enable, and p0vid[11:4] output double tag enable, and p1vid[11:4] field bits type description q3w 15:12 rw queue 3 weight see chapter 3.1.15 priority queue for more detail information. bpv 11:6 rw back to port vlan it is a per port function 0 b , doesn?t back to port vlan 1 b , backs to port vlan aovtp 5:0 rw admit only vlan_tagged packet it is a per port function 0 b , the port doesn?t check if the packets are vlan-tagged 1 b , the port drops the packets that carry no vid. (that is untagged packets or priority-tagged packets) idtep offset reset value input double tag enable, and p0vid[11:4] 28 h 0000 h field bits type description res 15:14 rw reserved res 13:8 rw reserved p0vid_11_4 7:0 rw p0vid[11:4] vid bit 11 ~ 4 fo port 0 odtep offset reset value output double tag enable, and p1vid[11:4] 29 h 0000 h uz 4: uz %39 uz $2973 uz 5hv uz 5hv uz 39,'bb
data sheet 121 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description output tag bypass, and p2vid[11:4] p3vid[11:4], and p4vid[11:4] field bits type description res 15:14 rw reserved res 13:12 rw reserved res 11:8 rw reserved p1vid_11_4 7:0 rw p1vid[11:4] vid bit 11 ~ 4 of port 1. otbp offset reset value output tag bypass, and p2vid[11:4] 2a h 3f00 h field bits type description res 15:14 rw reserved otbe 13:8 rw output tag bypass enable it?s a per port function. see chapter 3.1.14.12 egress tag rule for more detailed information. p2vid_11_4 7:0 rw p2vid[11:4] vid bit 11 ~ 4 of port 2. p11_4 offset reset value p3vid[11:4], and p4vid[11:4] 2b h 0000 h uz 5hv uz 5hv uz 5hv uz 39,'bb uz 5hv uz 27%( uz 39,'bb uz 39,'bb uz 39,'bb
samurai-6m/mx adm6996m/mx registers description data sheet 122 rev. 1.31, 2005-11-25 reserved address control, and p5vid[11:4] phy control register field bits type description p4vid_11_4 15:8 rw p4vid[11:4] vid bit 11 ~ 4 of port 4. p3vid_11_4 7:0 rw p3vid[11:4] vid bit 11 ~ 4 of port 3. racp offset reset value reserved address control, and p5vid[11:4] 2c h d000 h field bits type description ama3 15 rw action of mac address 3 the action of mac address = 0180c2000010 h ~ 0180c20000ff h ama2 14 rw action of mac address 2 the action of mac address = 0180c2000002 h ~ 0180c200000f h ama1 13 rw action of mac address 1 the action of mac address = 0180c2000001 h ama0 12 rw action of mac address 0 the action of mac address = 0180c2000000 h tag_shift 11:8 rw tag shift p5vid_11_4 7:0 rw p5vid[11:4] vid bit 11 ~ 4 of port 5 phyc offset reset value phy control register 2d h 4442 h uz $0$ uz $0$ uz $0$ uz $0$ uz 7$*b6+,)7 uz 39,'bb uz &,&' uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv
data sheet 123 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description adm tag ether type phy restart register field bits type description cicd 15 rw chip id check disable 0 b , checks chip id in 32 bit sdc/sdo 1 b , doesn?t check chip id in 32 bit sdc/sdio res 14 rw reserved res 13 rw reserved res 12:11 rw reserved res 10 rw reserved res 9 rw reserved res 8 rw reserved res 7 rw reserved res 6 rw reserved res 5 rw reserved res 4 rw reserved res 3:2 rw reserved res 1:0 rw reserved atet offset reset value adm tag ether type 2e h 0000 h field bits type description atet 15:0 rw adm tag ether type this value is used by the user to define their ether-type. when special tag receive is enabled, samurai-6m/6mx (adm6996m/mx) checks the packets on the cpu port to see if the two bytes following the sa are the same as adm tag ether type . if they are different, samurai-6m/6mx (adm6996m/mx) bypasses the special tag. if the same, samurai- 6m/6mx (adm6996m/mx) will use the value in the special tag to do switching decisions . pr offset reset value phy restart register 2f h 0000 h uz $7(7
samurai-6m/mx adm6996m/mx registers description data sheet 124 rev. 1.31, 2005-11-25 miscellaneous register field bits type description restart 15:0 rw restart samurai-6m/6mx (adm6996m/mx) writes this register to restart all the phys in the switch. the value written is not important. misc offset reset value miscellaneous register 30 h 0987 h field bits type description res 15 rw reserved res 14 rw reserved res 13 rw reserved p4 12 rw port 4 led mode 0 b , linkact/dupcol/speed. 1 b , link/act/speed. res 11 rw reserved res 10 rw reserved dhcol_led_ en 9rw dual speed hub col_led enable 0 b , normal led display. 1 b , dual speed hub led display. port0 col led: 10m col led. port1 col led: 100m col led. dp 8 rw drop packets drop packets when the link partner does not follow the pause protocol. 0 b , disable. 1 b , enable to drop packets. b7rw bypass bypass tag/untag function. 0 b , disable. 1 b , enable to bypass tag/untag function res 6 rw reserved uz 5(67$57 uz 5hv uz 5hv uz 5hv uz 3 uz 5hv uz 5hv uz '+&2 /b/ uz '3 uz % uz 5hv uz 0&(% uz 5hv uz 5hv uz 5hv uz 5hv uz 5hv
data sheet 125 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description basic bandwidth control register 0 basic bandwidth control register 1 mceb 5 rw mac clone enable bits select 0 b , select 1 bit mac clone function. 1 b , select 2 bits mac clone function. res 4 rw reserved res 3 rw reserved res 2 rw resreved res 1 rw reserved res 0 rw reserved bbc0 offset reset value basic bandwidth control register 0 31 h 0000 h field bits type description r3bw_th1 15 rw port 3 receive bandwidth maximum[3]. see register 0033 h , p3rbce for more details. r3bw_th0 14:12 rw port 3 receive bandwidth configuration see register 0033 h , p3rbce for more details. r2bw_th1 11 rw port 2 receive bandwidth maximum[3]. see register 0033 h , p2rbce for more details. r2bw_th0 10:8 rw port 2 receive bandwidth configuration see register 0033 h , p2rbce for more details. r1bw_th1 7 rw port 1 receive bandwidth maximum[3]. see register 0033 h , p1rbce for more details. r1bw_th0 6:4 rw port 1 receive bandwidth configuration see register 0033 h , p1rbce for more details. r0bw_th1 3 rw port 0 receive bandwidth maximum[3]. see register 0033 h , p0rbce for more details. r0bw_th0 2:0 rw port 0 receive bandwidth configuration see register 0033 h , p0rbce for more details. bbc1 offset reset value basic bandwidth control register 1 32 h 0000 h field bits type description uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+
samurai-6m/mx adm6996m/mx registers description data sheet 126 rev. 1.31, 2005-11-25 bandwidth control enable register field bits type description t1bw_th1 15 rw port 1 transmit bandwidth maximum[3]. see register 0033 h , p1tbce for more details. t1bw_th0 14:12 rw port 1 transmit bandwidth maximum[2:0]. see register 0033 h , p1tbce for more details. t0bw_th1 11 rw port 0 transmit bandwidth maximum[3]. see register 0033 h , p0tbce for more details. t0bw_th0 10:8 rw port 0 transmit bandwidth maximum[2:0]. see register 0033 h , p0tbce for more details. r5bw_th1 7 rw port 5 receive bandwidth maximum[3]. see register 0033 h , p5rbce for more details. r5bw_th0 6:4 rw port 5 receive bandwidth configuration see register 0033 h , p5rbce for more details. r4bw_th1 3 rw port 4 receive bandwidth maximum[3]. see register 0033 h , p4rbce for more details. r4bw_th0 2:0 rw port 4 receive bandwidth configuration see register 0033 h , p4rbce for more details. bce offset reset value bandwidth control enable register 33 h 0000 h field bits type description ipcp 15 rw invert p4 clock in pcs 0 d , disable 1 d , enable clc 14 rw check the length of crs 0 d , enable 1 d , disable res 13 rw reserved uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 5%: b7+ uz 5%:b7+ uz 5%: b7+ uz 5%:b7+ uz ,3&3 uz &/& uz 5hv uz $1%& ( uz 37% &( uz 37% &( uz 37% &( uz 35% &( uz 35% &( uz 35% &( uz 37% &( uz 35% &( uz 37% &( uz 35% &( uz 37% &( uz 35% &(
data sheet 127 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description anbce 12 rw samurai-6m/6mx (adm6996m/mx) new bandwidth control enable 0 b , disable 1 b , enable p5tbce 11 rw port 5 transmit bandwidth control enable the transmitted bandwidth is { t5bw_th3 , t5bw_th2 , t5bw_th1 , t5bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p4tbce 10 rw port 4 transmit bandwidth control enable the transmitted bandwidth is { t4bw_th3 , t4bw_th2 , t4bw_th1 , t4bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p3tbce 9 rw port 3 transmit bandwidth control enable the transmitted bandwidth is { t3bw_th3 , t3bw_th2 , t3bw_th1 , t3bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p5rbce 8 rw port 5 receive bandwidth control enable the received bandwidth is { r5bw_th3 , r5bw_th2 , r5bw_th1 , r5bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p4rbce 7 rw port 4 receive bandwidth control enable the received bandwidth is { r4bw_th3 , r4bw_th2 , r4bw_th1 , r4bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p3rbce 6 rw port 3 receive bandwidth control enable the received bandwidth is { r3bw_th3 , r3bw_th2 , r3bw_th1 , r3bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p2tbce 5 rw port 2 transmit bandwidth control enable the transmitted bandwidth is { t2bw_th3 , t2bw_th2 , t2bw_th1 , t2bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p2rbce 4 rw port 2 receive bandwidth control enable the received bandwidth is { r2bw_th3 , r2bw_th2 , r2bw_th1 , r2bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p1tbce 3 rw port 1 transmit bandwidth control enable the transmitted bandwidth is { t1bw_th3 , t1bw_th2 , t1bw_th1 , t1bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable field bits type description
samurai-6m/mx adm6996m/mx registers description data sheet 128 rev. 1.31, 2005-11-25 extended bandwidth control register 0 p1rbce 2 rw port 1 receive bandwidth control enable the received bandwidth is { r1bw_th3 , r1bw_th2 , r1bw_th1 , r1bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p0tbce 1 rw port 0 transmit bandwidth control enable the transmitted bandwidth is { t0bw_th3 , t0bw_th2 , t0bw_th1 , t0bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable p0rbce 0 rw port 0 receive bandwidth control enable the received bandwidth is { r0bw_th3 , r0bw_th2 , r0bw_th1 , r0bw_th0 , 000000 b } kbit/s. k = 1000. 0 b , disable 1 b , enable ebc0 offset reset value extended bandwidth control register 0 34 h 0000 h field bits type description t5bw_th1 15 rw port 5 transmit bandwidth maximum[3]. see register 0033 h , p5tbce for more details. t5bw_th0 14:12 rw port 5 transmit bandwidth maximum[2:0]. see register 0033 h , p5tbce for more details. t4bw_th1 11 rw port 4 transmit bandwidth maximum[3]. see register 0033 h , p4tbce for more details. t4bw_th0 10:8 rw port 4 transmit bandwidth maximum[2:0]. see register 0033 h , p4tbce for more details. t3bw_th1 7 rw port 3 transmit bandwidth maximum[3]. see register 0033 h , p3tbce for more details. t3bw_th0 6:4 rw port 3 transmit bandwidth maximum[2:0]. see register 0033 h , p3tbce for more details. t2bw_th1 3 rw port 2 transmit bandwidth maximum[3]. see register 0033 h , p2tbce for more details. t2bw_th0 2:0 rw port 2 transmit bandwidth maximum[2:0]. see register 0033 h , p2tbce for more details. field bits type description uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+ uz 7%: b7+ uz 7%:b7+
data sheet 129 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description extended bandwidth control register 1 extended bandwidth control register 2 ebc1 offset reset value extended bandwidth control register 1 35 h 0000 h field bits type description r3bw_th2 15:12 rw port 3 receive bandwidth maximum[7:4]. see register 0033 h , p3rbce for more details. r2bw_th2 11:8 rw port 2 receive bandwidth maximum[7:4]. see register 0033 h , p2rbce for more details. r1bw_th2 7:4 rw port 1 receive bandwidth maximum[7:4]. see register 0033 h , p1rbce for more details. r0bw_th2 3:0 rw port 0 receive bandwidth maximum[7:4]. see register 0033 h , p0rbce for more details. ebc2 offset reset value extended bandwidth control register 2 36 h 0000 h field bits type description t1bw_th2 15:12 rw port 1 transmit bandwidth maximum[7:4] see register 0033 h , p1tbce for more details. t0bw_th2 11:8 rw port 0 transmit bandwidth maximum[7:4]. see register 0033 h , p0tbce for more details. r5bw_th2 7:4 rw port 5 receive bandwidth maximum[7:4]. see register 0033 h , p5rbce for more details. r4bw_th2 3:0 rw port 4 receive bandwidth maximum[7:4]. see register 0033 h , p4rbce for more details. uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 7%:b7+ uz 7%:b7+ uz 5%:b7+ uz 5%:b7+
samurai-6m/mx adm6996m/mx registers description data sheet 130 rev. 1.31, 2005-11-25 extended bandwidth control register 3 extended bandwidth control register 4 ebc3 offset reset value extended bandwidth control register 3 37 h 0000 h field bits type description t5bw_th2 15:12 rw port 5 transmit bandwidth maximum[7:4]. see register 0033 h , p5tbce for more details. t4bw_th2 11:8 rw port 4 transmit bandwidth maximum[7:4]. see register 0033 h , p4tbce for more details. t3bw_th2 7:4 rw port 3 transmit bandwidth maximum[7:4]. see register 0033 h , p3tbce for more details. t2bw_th2 3:0 rw port 2 transmit bandwidth maximum[7:4]. see register 0033 h , p2tbce for more details. ebc4 offset reset value extended bandwidth control register 4 38 h 0000 h field bits type description fmdix0 15 rw port 0 mdix control this bit can be used for port 0 mdi/mdix selection. it is useful when port 0 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b , using mdi 1 b , using mdix r4bw_th3 14:12 rw port 4 receive bandwidth maximum[10:8]. see register 0033 h , p4rbce for more details. r3bw_th3 11:9 rw port 3 receive bandwidth maximum[10:8]. see register 0033 h , p3rbce for more details. uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz )0', ; uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+ uz 5%:b7+
data sheet 131 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description extended bandwidth control register 5 default vlan member and extended bandwidth control register 6 r2bw_th3 8:6 rw port 2 receive bandwidth maximum[10:8]. see register 0033 h , p2rbce for more details. r1bw_th3 5:3 rw port 1 receive bandwidth maximum[10:8]. see register 0033 h , p1rbce for more details. r0bw_th3 2:0 rw port 0 receive bandwidth maximum[10:8]. see register 0033 h , p0rbce for more details. ebc5 offset reset value extended bandwidth control register 5 39 h 0000 h field bits type description fmdix1 15 r port 1 mdix control this bit can be used for port 1 mdi/mdix selection. it is useful when port 1 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b , using mdi 1 b , using mdix t3bw_th3 14:12 rw port 3 transmit bandwidth maximum[10:8]. see register 0033 h , p3tbce for more details. t2bw_th3 11:9 rw port 2 transmit bandwidth maximum[10:8]. see register 0033 h , p2tbce for more details. t1bw_th3 8:6 rw port 1 transmit bandwidth maximum[10:8]. see register 0033 h , p1tbce for more details. t0bw_th3 5:3 rw port 0 transmit bandwidth maximum[10:8]. see register 0033 h , p0tbce for more details. r5bw_th3 2:0 rw port 5 receive bandwidth maximum[10:8]. see register 0033 h , p5rbce for more details. dvmebc6 offset reset value default vlan member and extended bandwidth control register 6 3a h 0fc0 h field bits type description u )0', ; uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 7%:b7+ uz 5%:b7+
samurai-6m/mx adm6996m/mx registers description data sheet 132 rev. 1.31, 2005-11-25 new storm register 0 field bits type description res 15:12 rw reserved dvm 11:6 rw default vlan member t5bw_th3 5:3 rw port 5 transmit bandwidth maximum[10:8]. see register 0033 h , p5tbce for more details. t4bw_th3 2:0 rw port 4 transmit bandwidth maximum[10:8]. see register 0033 h , p4tbce for more details. ns0 offset reset value new storm register 0 3b h 0000 h field bits type description res 15 r reserved storm_dro p_en 14 rw storm drop enable 0 b , doesn?t drop in the storming period 1 b , drops in the storming period storm_en 13 rw storm enable 0 b , disable samurai-6m/6mx (adm6996m/mx) style broadcast storm protection 1 b , enable samurai-6m/6mx (adm6996m/mx) style broadcast storm protection storm_100_ th 12:0 rw 100m threshold see chapter 3.1.9 broadcast storm for more detailed information. it is used when all ports link up in the 100m. the upper bound is reached when the number of the packets received during the 50 ms is over 100m threshold. uz 5hv uz '90 uz 7%:b7+ uz 7%:b7+ u 5hv uz 6725 0b' uz 6725 0b(1 uz 67250bb7+
data sheet 133 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description new storm register 1 new reserve address control register 0 ns1 offset reset value new storm register 1 3c h 0000 h field bits type description fmdix4 15 rw port 4 mdix control this bit can be used for port 4 mdi/mdix selection. it is useful when port 4 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b , using mdi 1 b , using mdix fmdix3 14 rw port 3 mdix control this bit can be used for port 3 mdi/mdix selection. it is useful when port 3 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b , using mdi 1 b , using mdix fmdix2 13 rw port 2 mdix control this bit can be used for port 2 mdi/mdix selection. it is useful when port 2 crossover auto detect is disabled and 16 bits management interface (sdc/sdio) is used. 0 b , using mdi 1 b , using mdix storm_10_t h 12:0 rw 10m threshold see chapter 3.1.9 broadcast storm for more detailed information. it is used when one of ports link up in the 10m. the upper bound is reached when the number of the packets received during the 50 ms is over 10m threshold. nrac0 offset reset value new reserve address control register 0 3d h 00fd h uz )0', ; uz )0', ; uz )0', ; uz 67250bb7+ uz 157% uz 3* uz 35,b6 uz 35,b% uz 533 uz 533 uz *33 uz 533 uz 533 uz 333 uz 633 uz %33
samurai-6m/mx adm6996m/mx registers description data sheet 134 rev. 1.31, 2005-11-25 field bits type description nrtb 15:14 rw new reserve txtag for bpdu 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged pg 13:12 rw pri for gxrp 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 pri_s 11:10 rw pri for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 pri_b 9:8 rw pri for bpdu 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 r3pp 7 rw reser_r3 pass portmap 0 b , reser_r3 pass portmap is 000000 b 1 b , reser_r3 pass pormap is 111111 b r2pp 6 rw reser_r2 pass portmap 0 b , reser_r2 pass portmap is 000000 b 1 b , reser_r2 pass pormap is 111111 b gpp 5 rw gxrp pass portmap 0 b , gxrp pass portmap is 000000 b 1 b , gxrp pass pormpap is 111111 b r1pp 4 rw reser_r1 pass portmap 0 b , reser_r1 pass portmap is 000000 b 1 b , reser_r1 pass portmap is 111111 b r0pp 3 rw reser_r0 pass portmap 0 b , reser_r0 pass portmap is 000000 b 1 b , reser_r0 pass portmap is 111111 b ppp 2 rw pae pass portmap 0 b , pae pass portmap is 000000 b 1 b , pae pass portpap is 111111 b spp 1 rw slow pass portmap 0 b , slow pass portmap is 000000 b 1 b , slow pass portpap is 111111 b bpp 0 rw bpdu pass portmap 0 b , bpdu pass portmap is 000000 b 1 b , bpdu pass portpap is 111111 b
data sheet 135 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description new reserve address control register 1 nrac1 offset reset value new reserve address control register 1 3e h 0000 h field bits type description mca1 15 rw mac control action 1 mac control action when opcode is 01 h 0 b , the same as mac control action when opcode is not 01 h 1 b , discards mca2 14:13 rw mac control action 2 mac control action whenopcode is not 01 h 00 b , defaults output ports 01 b , discards 10 b , if the receiving port is the cpu port, forward it to the default output ports. if the receiving port is not the cpu port, forward it to the cpu port 11 b , forwards to the default output ports except the cpu port nrmg 12 rw new reserve management for gxrp 0 b , doesn?t identify as management packets 1 b , identifies as management packets nrms 11 rw new reserve management for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b , doesn?t identify as management packets 1 b , identifies as management packets mrmb 10 rw new reserve management for bpdu 0 b , doesn?t identify as management packets 1 b , identifies as management packets nrsg 9 rw new reserve span.for gxrp 0 b , doesn?t identify as management packets 1 b , identifies as management packets nrss 8 rw new reserve span for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b , doesn?t identify as span packets 1 b , identifies as span packets nrsb 7 rw new reserve span for bpdu 0 b , doesn?t identify as span packets 1 b , identifies as span packets nrcg 6 rw new reserve cross_vlan for gxrp 0 b , follows vlan 1 b , crosses vlan uz 0&$ uz 0&$ uz 150* uz 1506 uz 050% uz 156* uz 1566 uz 156% uz 15&* uz 15&6 uz 15&% uz 157* uz 1576
samurai-6m/mx adm6996m/mx registers description data sheet 136 rev. 1.31, 2005-11-25 hardware igmp control register nrcs 5 rw new reserve cross_vlan. for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 0 b , follows vlan 1 b , crosses vlan nrcb 4 rw new reserve cross_vlan for bpdu 0 b , follows vlan 1 b , crosses vlan nrtg 3:2 rw new reserve txtag for gxrp 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged nrts 1:0 rw new reserve txtag for slow/pae/reser_r0/reser_r1/reser_r2/reser_r3 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged hic offset reset value hardware igmp control register 3f h 7c80 h field bits type description qi 15:8 rw query interval the register is used to define query_interval when hardware based igmp snooping function is enabled (000c h , hise ). the automatically learned router port will be aged out if no igmp query frame received from the router port for (query_interval * robust variable) seconds. rv 7:6 rw robust variable the register is used to define robust_variable when hardware based igmp snooping function is enabled (000c h , hise ). 00 b , reserved 01 b , 1 time 10 b , 2 times 11 b , 3 times field bits type description uz 4, uz 59 uz '53
data sheet 137 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description 4.2 eeprom extended registers vlan filter 0 low similar registers drp 5:0 rw default router portmap the register is used to define static router port when hardware based igmp snooping function and default router port function are enabled (000c h , hise & hidre ). vf0l offset reset value vlan filter 0 low 40 h 003f h field bits type description fid 15:12 rw fid the forwarding or learning group that the vid is assigned. tm 11:6 rw tagged member these bits indicate which ports are associated with the vid should transmit tagged packets.tagged member[x] description. 0 b , port x should transmit untagged packets 1 b , port x should transmit tagged packets m5:0rw member these bits indicate which ports are the members of the vlan.member[x] description. 0 b , port x is not a vlan member 1 b , port x is a vlan member table 57 vfxl registers register short name register long name offset address page number vf1l vlan filter 1 low 42 h vf2l vlan filter 2 low 44 h vf3l vlan filter 3low 46 h vf4l vlan filter 4 low 48 h vf5l vlan filter 5 low 4a h vf6l vlan filter 6 low 4c h vf7l vlan filter 7 low 4e h field bits type description uz ),' uz 70 uz 0
samurai-6m/mx adm6996m/mx registers description data sheet 138 rev. 1.31, 2005-11-25 vlan filter 0 high similar registers all vfxh registers have the same structure and characteristics, see vf0h . the offset addresses of the other vfxh registers are listed in table 58 . vf8l vlan filter 8 low 50 h vf9l vlan filter 9 low 52 h vf10l vlan filter 10 low 54 h vf11l vlan filter 11 low 56 h vf12l vlan filter 12 low 58 h vf13l vlan filter 13 low 5a h vf14l vlan filter 14 low 5c h vf15l vlan filter 15 low 5e h vf0h offset reset value vlan filter 0 high 41 h 8001 h field bits type description vv 15 rw vlan_valid 0 b , vlan filter is not valid 1 b , vlan filter is valid vp 14:12 rw vlan pri it indicates the vlan priority that is associated with vid. vid 11:0 rw vid it indicates the vlan id that is associated with fid, tagged member, member and vlan pri. table 58 vfxh registers register short name register long name offset address page number vf1h vlan filter 1 high 43 h vf2h vlan filter 2 high 45 h vf3h vlan filter 3 high 47 h vf4h vlan filter 4 high 49 h vf5h vlan filter 5 high 4b h vf6h vlan filter 6 high 4d h table 57 vfxl registers (cont?d) register short name register long name offset address page number uz 99 uz 93 uz 9,'
data sheet 139 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description type filter 0 similar registers all tfx registers have the same structure and characteristics, see tf0 . the offset addresses of the other tfx registers are listed in table 59 . vf7h vlan filter 7 high 4f h vf8h vlan filter 8 high 51 h vf9h vlan filter 9 high 53 h vf10h vlan filter 10 high 55 h vf11h vlan filter 11 high 57 h vf12h vlan filter 12 high 59 h vf13h vlan filter 13 high 5b h vf14h vlan filter 14 high 5d h vf15h vlan filter 15 high 5f h tf0 offset reset value type filter 0 60 h 0000 h field bits type description vcet 15:0 rw value compared with ether-type table 59 tfx registers register short name register long name offset address page number tf1 type filter 1 61 h tf2 type filter 2 62 h tf3 type filter 3 63 h tf4 type filter 4 64 h tf5 type filter 5 65 h tf6 type filter 6 66 h tf7 type filter 7 67 h table 58 vfxh registers (cont?d) register short name register long name offset address page number uz 9&(7
samurai-6m/mx adm6996m/mx registers description data sheet 140 rev. 1.31, 2005-11-25 protocol filter 1 and 0 similar registers all pfx registers have the same structure and characteristics, see pf_1_0 . the offset addresses of the other pfx registers are listed in table 60 . service priority mapping 0 pf_1_0 offset reset value protocol filter 1 and 0 68 h 0000 h field bits type description pfr1 15:8 rw value compared with protocol in ip header (protocol filter 1, 3, 5, 7) pfr0 7:0 rw value compared with protocol in ip header (protocol filter 0, 2, 4, 6) table 60 pfx registers register short name register long name offset address page number pf_3_2 protocol filter 3 and 2 68 h pf_5_4 protocol filter 5 and 4 69 h pf_7_6 protocol filter 7 and 6 6a h spm0 offset reset value service priority mapping 0 6c h 0000 h field bits type description pq7 15:14 rw priority queue 7 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000111 b . uz 3)5 uz 3)5 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
data sheet 141 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description service priority mapping 1 pq6 13:12 rw priority queue 6 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000110 b . pq5 11:10 rw priority queue 5 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000101 b . pq4 9:8 rw priority queue 4 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000100 b . pq3 7:6 rw priority queue 3 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000011 b . pq2 5:4 rw priority queue 2 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000010 b . pq1 3:2 rw priority queue 1 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000001 b . pq0 1:0 rw priority queue 0 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 000000 b . 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 spm1 offset reset value service priority mapping 1 6d h 0000 h field bits type description pqf 15:14 rw priority queue f the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001111 b pqe 13:12 rw priority queue e the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001110 b field bits type description uz 34) uz 34( uz 34' uz 34& uz 34% uz 34$ uz 34 uz 34
samurai-6m/mx adm6996m/mx registers description data sheet 142 rev. 1.31, 2005-11-25 service priority mapping 2 pqd 11:10 rw priority queue d the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001101 b pqc 9:8 rw priority queue c the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001100 b pqb 7:6 rw priority queue b the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001011 b pqa 5:4 rw priority queue a the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001010 b pq9 3:2 rw priority queue 9 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001001 b pq8 1:0 rw priority queue 8 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 001000 b spm2 offset reset value service priority mapping 2 6e h 0000 h field bits type description pq17 15:14 rw priority queue 17 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010111 b pq16 13:12 rw priority queue 16 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010110 b pq15 11:10 rw priority queue 15 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010101 b pq14 9:8 rw priority queue 14 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010100 b field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
data sheet 143 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description service priority mapping 3 pq13 7:6 rw priority queue 13 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010011 b pq12 5:4 rw priority queue 12 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010010 b pq11 3:2 rw priority queue 11 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010001 b pq10 1:0 rw priority queue 10 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 010000 b spm3 offset reset value service priority mapping 3 6f h 0000 h field bits type description pq1f 15:14 rw priority queue 1f the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011111 b pq1e 13:12 rw priority queue 1e the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011110 b pq1d 11:10 rw priority queue 1d the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011101 b pq1c 9:8 rw priority queue 1c the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011100 b pq1b 7:6 rw priority queue 1b the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011011 b pq1a 5:4 rw priority queue 1a the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011010 b field bits type description uz 34) uz 34( uz 34' uz 34& uz 34% uz 34$ uz 34 uz 34
samurai-6m/mx adm6996m/mx registers description data sheet 144 rev. 1.31, 2005-11-25 service priority mapping 4 pq19 3:2 rw priority queue 19 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011001 b pq18 1:0 rw priority queue 18 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 011000 b spm4 offset reset value service priority mapping 4 70 h 0000 h field bits type description pq27 15:14 rw priority queue 27 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100111 b pq26 13:12 rw priority queue 26 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100110 b pq25 11:10 rw priority queue 25 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100101 b pq24 9:8 rw priority queue 24 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100100 b pq23 7:6 rw priority queue 23 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100011 b pq22 5:4 rw priority queue 22 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100010 b pq21 3:2 rw priority queue 21 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100001 b pq20 1:0 rw priority queue 20 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 100000 b field bits type description uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34
data sheet 145 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description service priority mapping 5 service priority mapping 6 spm5 offset reset value service priority mapping 5 71 h 0000 h field bits type description pq2f 15:14 rw priority queue 2f the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101111 b pq2e 13:12 rw priority queue 2e the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101110 b pq2d 11:10 rw priority queue 2d the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101101 b pq2c 9:8 rw priority queue 2c the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101100 b pq2b 7:6 rw priority queue 2b the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101011 b pq2a 5:4 rw priority queue 2a the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101010 b pq29 3:2 rw priority queue 29 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101001 b pq28 1:0 rw priority queue 28 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 101000 b spm6 offset reset value service priority mapping 6 72 h 0000 h uz 34) uz 34( uz 34' uz 34& uz 34% uz 34$ uz 34 uz 34
samurai-6m/mx adm6996m/mx registers description data sheet 146 rev. 1.31, 2005-11-25 service priority mapping 7 field bits type description pq37 15:14 rw priority queue 37 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110111 b pq36 13:12 rw priority queue 36 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110110 b pq35 11:10 rw priority queue 35 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110101 b pq34 9:8 rw priority queue 34 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110100 b pq33 7:6 rw priority queue 33 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110011 b pq32 5:4 rw priority queue 32 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110010 b pq31 3:2 rw priority queue 31 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110001 b pq30 1:0 rw priority queue 30 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 110000 b spm7 offset reset value service priority mapping 7 73 h 0000 h uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34 uz 34) uz 34( uz 34' uz 34& uz 34% uz 34$ uz 34 uz 34
data sheet 147 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description reserve action for 0180c2000001~0180c2000000 field bits type description pq3f 15:14 rw priority queue 3f the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111111 b pq3e 13:12 rw priority queue 3e the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111110 b pq3d 11:10 rw priority queue 3d the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111101 b pq3c 9:8 rw priority queue 3c the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111100 b pq3b 7:6 rw priority queue 3b the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111011 b pq3a 5:4 rw priority queue 3a the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111010 b pq39 3:2 rw priority queue 39 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111001 b pq38 1:0 rw priority queue 38 the value in this field is used as the priority queue when the significant 6 bits in the ipv4 tos/ipv6 traffic class are 111000 b ra_01_00 offset reset value reserve action for 0180c2000001~0180c2000000 74 h 0000 h field bits type description ra01_valid 15 rw valid bit for 0180c2000001 0 b , not valid 1 b , valid ra01_span 14 rw span bit for 0180c2000001 0 b , doesn?t identify as the span packet 1 b , identifies as the span packet uz 5$ b9$ uz 5$ b63 uz 5$ b0* uz 5$ b&9 uz 5$b7; 7$* uz 5$b$& 7 uz 5$ b9$ uz 5$ b63 uz 5$ b0* uz 5$ b&9 uz 5$b7; 7$* uz 5$b$& 7
samurai-6m/mx adm6996m/mx registers description data sheet 148 rev. 1.31, 2005-11-25 similar registers all rax registers have the same structure and characteristics, see ra_01_00 . the offset addresses of the other rax registers are listed in table 61 . ra01_mg 13 rw management bit for 0180c2000001 0 b , doesn?t identify as the management packet 1 b , identifies as the management packet ra01_cv 12 rw cross_vlan bit for 0180c2000001 0 b , doesn?t identify as the cross_vlan packet 1 b , identifies as the cross_vlan packet ra01_txtag 11:10 rw txtag bit for 0180c2000001 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged ra01_act 9:8 rw action bit for 0180c2000001 00 b , portmap is 111111 b 01 b , portmap is 000000 b 10 b , portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then reserve portmap contains all the ports, excluding the cpu port 11 b , portmap contains all the ports, excluding the cpu port ra00_valid 7 rw valid bit for 0180c2000000 0 b , not valid 1 b , valid ra00_span 6 rw span bit for 0180c2000000 0 b , doesn?t identify as the span packet 1 b , identifies as the span packet ra00_mg 5 rw management bit for 0180c2000000 0 b , doesn?t identify as the management packet 1 b , identifies as the management packet ra00_cv 4 rw cross_vlan bit for 0180c2000000 0 b , doesn?t identify as the cross_vlan packet 1 b , identifies as the cross_vlan packet ra00_txtag 3:2 rw txtag bit for 0180c2000000 00 b , system default tag 01 b , unmodified 10 b , always tagged 11 b , always untagged ra00_act 1:0 rw action bit for 0180c2000000 00 b , portmap is 111111 b 01 b , portmap is 000000 b 10 b , portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then reserve portmap contains all the ports, excluding the cpu port 11 b , portmap contains all the ports, excluding the cpu port field bits type description
data sheet 149 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description table 61 rax registers register short name register long name offset address page number ra_03_02 reserve action for 0180c2000003~0180c2000002 75 h ra_05_04 reserve action for 0180c2000005~0180c2000004 76 h ra_07_06 reserve action for 0180c2000007~0180c2000006 77 h ra_09_08 reserve action for 0180c2000009~0180c2000008 78 h ra_0b_0a reserve action for 0180c200000b~0180c200000a 79 h ra_0d_0c reserve action for 0180c200000d~0180c200000c 7a h ra_0f_0e reserve action for 0180c200000f~0180c200000e 7b h ra_11_10 reserve action for 0180c2000011~0180c2000010 7c h ra_13_12 reserve action for 0180c2000013~0180c2000012 7d h ra_15_14 reserve action for 0180c2000015~0180c2000014 7e h ra_17_16 reserve action for 0180c2000017~0180c2000016 7f h ra_19_18 reserve action for 0180c2000019~0180c2000018 80 h ra_1b_1a reserve action for 0180c200001b~0180c200001a 81 h ra_1d_1c reserve action for 0180c200001d~0180c200001c 82 h ra_1f_1e reserve action for 0180c200001f~0180c200001e 83 h ra_21_20 reserve action for 0180c2000021~0180c2000020 84 h ra_23_22 reserve action for 0180c2000023~0180c2000022 85 h ra_25_24 reserve action for 0180c2000025~0180c2000024 86 h ra_27_26 reserve action for 0180c2000027~0180c2000026 87 h ra_29_28 reserve action for 0180c2000029~0180c2000028 88 h ra_2b_2a reserve action for 0180c200002b~0180c200002a 89 h
samurai-6m/mx adm6996m/mx registers description data sheet 150 rev. 1.31, 2005-11-25 tcp/udp filter 0 similar registers all tufx registers have the same structure and characteristics, see tuf0 . the offset addresses of the other tufx registers are listed in table 64 . type filter action ra_2d_2c reserve action for 0180c200002d~0180c200002c 8a h ra_2f_2e reserve action for 0180c200002f~0180c200002e 8b h tuf0 offset reset value tcp/udp filter 0 8c h 0000 h field bits type description val_comp 15:0 rw value compared with the destinat ion port number in the tcp/udp header table 62 tufx registers register short name register long name offset address page number tuf1 tcp/udp filter 1 8d h tuf2 tcp/udp filter 2 8e h tuf3 tcp/udp filter 3 8f h tuf4 tcp/udp filter 4 90 h tuf5 tcp/udp filter 5 91 h tuf6 tcp/udp filter 6 92 h tuf7 tcp/udp filter 7 93 h tfa offset reset value type filter action 94 h 0000 h table 61 rax registers (cont?d) register short name register long name offset address page number uz 9$/b&203
data sheet 151 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description protocol filter action field bits type description atf7 15:14 rw action for type filter 7 see register 0094 h , atf0 for more details. atf6 13:12 rw action for type filter 6 see register 0094 h , atf0 for more details. atf5 11:10 rw action for type filter 5 see register 0094 h , atf0 for more details. atf4 9:8 rw action for type filter 4 see register 0094 h , atf0 for more details. atf3 7:6 rw action for type filter 3 see register 0094 h , atf0 for more details. atf2 5:4 rw action for type filter 2 see register 0094 h , atf0 for more details. atf1 3:2 rw action for type filter 1 see register 0094 h , atf0 for more details. atf0 1:0 rw action for type filter 0 00 b , type portmap is default output ports 01 b , type portmap is 000000 b 10 b , type portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains default output ports , excluding the cpu port 11 b , type portmap contains default output port, excluding the cpu port pfa offset reset value protocol filter action 95 h 0000 h field bits type description apf7 15:14 rw action for protocol filter 7 see register 0095 h , apf0 for more details. uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $7) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3) uz $3)
samurai-6m/mx adm6996m/mx registers description data sheet 152 rev. 1.31, 2005-11-25 tcp/udp action 0 apf6 13:12 rw action for protocol filter 6 see register 0095 h , apf0 for more details. apf5 11:10 rw action for protocol filter 5 see register 0095 h , apf0 for more details. apf4 9:8 rw action for protocol filter 4 see register 0095 h , apf0 for more details. apf3 7:6 rw action for protocol filter 3 see register 0095 h , apf0 for more details. apf2 5:4 rw action for protocol filter 2 see register 0095 h , apf0 for more details. apf1 3:2 rw action for protocol filter 1 see register 0095 h , apf0 for more details. apf0 1:0 rw action for protocol filter 0 00 b , protocol portmap is default output ports 01 b , protocol portmap is 000000 b 10 b , protocol portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains default output ports, excluding the cpu port 11 b , protocol portmap contains default output ports, excluding the cpu port tua0 offset reset value tcp/udp action 0 96 h 0000 h field bits type description atuf3 15:14 rw action for tcp/udp filter 3. see register 0096 h , atuf0 for more details. tupf3 13:12 rw tcp/udp pri for tcp/udp filter 3 see register 0096 h , tupf0 for more details. atuf2 11:10 rw action for tcp/udp filter 2 see register 0096 h , atuf0 for more details. tupf2 9:8 rw tcp/udp pri for tcp/udp filter 2 see register 0096 h , tupf0 for more details. atuf1 7:6 rw action for tcp/udp filter 1 see register 0096 h , atuf0 for more details. tupf1 5:4 rw tcp/udp pri for tcp/udp filter 1 see register 0096 h , tupf0 for more details. field bits type description uz $78) uz 783) uz $78) uz 783) uz $78) uz 783) uz $78) uz 783)
data sheet 153 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description tcp/udp action 1 atuf0 3:2 rw action for tcp/udp filter 0 00 b , protocol portmap is default output ports 01 b , protocol portmap is 000000 b 10 b , protocol portmap is the cpu port if the incoming port is not the cpu port. but if the incoming port is the cpu port, then type portmap contains default output ports, excluding the cpu port 11 b , protocol portmap contains default output ports, excluding the cpu port tupf0 1:0 rw tcp/udp pri for tcp/udp filter 0 00 b , queue 0 01 b , queue 1 10 b , queue 2 11 b , queue 3 tua1 offset reset value tcp/udp action 1 97 h 0000 h field bits type description atuf7 15:14 rw action for tcp/udp filter 7 see register 0096 h , atuf0 for more details. tupf7 13:12 rw tcp/udp pri for tcp/udp filter 7 see register 0096 h , tupf0 for more details. atuf6 11:10 rw action for tcp/udp filter 6 see register 0096 h , atuf0 for more details. tupf6 9:8 rw tcp/udp pri for tcp/udp filter 6 see register 0096 h , tupf0 for more details. atuf5 7:6 rw action for tcp/udp filter 5 see register 0096 h , atuf0 for more details. tupf5 5:4 rw tcp/udp pri for tcp/udp filter 5 see register 0096 h , tupf0 for more details. atuf4 3:2 rw action for tcp/udp filter 4 see register 0096 h , atuf0 for more details. tupf4 1:0 rw tcp/udp pri for tcp/udp filter 4 see register 0096 h , tupf0 for more details. field bits type description uz $78) uz 783) uz $78) uz 783) uz $78) uz 783) uz $78) uz 783)
samurai-6m/mx adm6996m/mx registers description data sheet 154 rev. 1.31, 2005-11-25 tcp/udp action 2 tua2 offset reset value tcp/udp action 2 98 h 0000 h field bits type description res 15:14 r reserved comp 13:12 rw compare tcp/udp source port or destination port 00 b , doesn?t compare 01 b , compares destination port 10 b , compares source port 11 b , compares destination port or source port p5i 11 rw port 5 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p4i 10 rw port 4 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p3i 9 rw port 3 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p2i 8 rw port 2 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p1i 7 rw port 1 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p0i 6 rw port 0 ip over tcp/udp 0 b , uses tcp/udp field when packets contain both tcp/udp and ip 1 b , uses ip field when packets contain both tcp/udp and ip p5t 5 rw port 5 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority p4t 4 rw port 4 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority p3t 3 rw port 3 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority u 5hv uz &203 uz 3, uz 3, uz 3, uz 3, uz 3, uz 3, uz 37 uz 37 uz 37 uz 37 uz 37 uz 37
data sheet 155 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description extended igmp control/special tag insert control p2t 2 rw port 2 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority p1t 1 rw port 1 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority p0t 0 rw port 0 tcp/udp prien 0 b , doesn?t use tcp/udp priority 1 b , uses tcp/udp priority eicstic offset reset value extended igmp control/special tag insert control 99 h 01ff h field bits type description res 15:10 rw reserved iac 9 rw include address change into po rt security interrupt source 0 b , doesn?t include 1 b , includes ins_ip 8 rw insert special tag in ip packet. (not in the type/protocol/tcpudp) 0 b , doesn?t insert 1 b , inserts ins_res 7 rw insert special tag in reserve packet. 0 b , doesn?t insert 1 b , inserts ins_arp 6 rw insert special tag in arp/rarp packet. 0 b , doesn?t insert 1 b , inserts ins_snoop 5 rw insert special tag in igmp/mld packet. 0 b , doesn?t insert 1 b , inserts ins_typ 4 rw insert special tag if type field matches with pre-defined rules. 0 b , doesn?t insert 1 b , inserts field bits type description uz 5hv uz ,$& uz ,16b ,3 uz ,16b 5(6 uz ,16b $53 uz ,16b 612 uz ,16b 7<3 uz ,16b 3527 uz ,16b 78 uz ,16b 0& uz ,16b '()
samurai-6m/mx adm6996m/mx registers description data sheet 156 rev. 1.31, 2005-11-25 interrupt enable register ins_prot 3 rw insert special tag if protocol field matches with pre-defined rules. 0 b , doesn?t insert 1 b , inserts ins_tu 2 rw insert special tag if port field matches with pre-defined rules. 0 b , doesn?t insert 1 b , inserts ins_mc 1 rw insert special tag in mac control packet. 0 b , doesn?t insert 1 b , inserts ins_def 0 rw insert special tag in the packets except those packets defined in bit 8 ~ 1. 0 b , doesn?t insert 1 b , inserts ie offset reset value interrupt enable register 9a h 0000 h field bits type description res 15:9 r reserved ltadie 8 rw leaning table access done interrupt enable 0 b , interrupt disable 1 b , interrupt enable psie 7:2 rw port security interrupt enable it?s a per port setting 0 b , interrupt disable 1 b , interrupt enable coie 1 rw counter overflow interrupt enable 0 b , interrupt disable 1 b , interrupt enable psie 0 rw port status in terrupt enable 0 b , interrupt disable 1 b , interrupt enable field bits type description u 5hv uz /7$' ,( uz 36,( uz &2,( uz 36,(
data sheet 157 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description interrupt status register security control register is offset reset value interrupt status register 9b h 0000 h field bits type description res 15:9 r reserved ltad 8 lhsc leaning table access done 0 b , access does not end 1 b , access end psv 7:2 lhsc port security violation it?s a per port setting 0 b , security did not violate 1 b , security violated co 1 lhsc counter overflow 0 b , overflow did not happen 1 b , overflow happened for any of the counters psc 0 lhsc port status change 0 b , no status (link, speed, duplex, flow control) changed for any port 1 b , status changed for any of 6 ports sc offset reset value security control register 9c h 0000 h field bits type description res 15:13 r reserved res 12:0 rw reserved u 5hv okvf /7$' okvf 369 okvf &2 okvf 36& u 5hv uz 5hv
samurai-6m/mx adm6996m/mx registers description data sheet 158 rev. 1.31, 2005-11-25 4.3 counter and switch status registers chip identifier 0 chip identifier 1 port status 0 ci0 offset reset value chip identifier 0 a0 h 1022 h field bits type description pc 15:4 ro product code[11:0] vn 3:0 ro version number ci1 offset reset value chip identifier 1 a1 h 0007 h field bits type description res 15:4 ro reserved pc 3:0 ro product code[ 15:12 ] ps0 offset reset value port status 0 a2 h 0000 h ur 3& ur 91 ur 5hv ur 3& ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6
data sheet 159 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description port status 1 field bits type description res 15:12 ro reserved p1fcs 11 ro port 1 flow control status 0 b , port 1 disables the full flow control/half back pressure function 1 b , port 1 enables the full flow control/half back pressure function p1ds 10 ro port 1 duplex status 0 b , port 1 operates in the half duplex 1 b , port 1 operates in the full duplex p1ss 9 ro port 1 speed status 0 b , port 1 operates in the 10m 1 b , port 1 operates in the 100m p1ls 8 ro port 1 link status 0 b , port 1 links down 1 b , port 1 links up res 7:4 ro reserved p0fcs 3 ro port 0 flow control status 0 b , port 0 disables the full flow control/half back pressure function 1 b , port 0 enables the full flow control/half back pressure function p0ds 2 ro port 0 duplex status 0 b , port 0 operates in the half duplex 1 b , port 0 operates in the full duplex p0ss 1 ro port 0 speed status 0 b , port 0 operates in the 10m 1 b , port 0 operates in the 100m p0ls 0 ro port 0 link status 0 b , port 0 links down 1 b , port 0 links up ps1 offset reset value port status 1 a3 h 0000 h field bits type description p4fcs 15 ro port 4 flow control status 0 b , port 4 disables the full flow control/half back pressure function 1 b , port 4 enables the full flow control/half back pressure function ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 3)& 6 ur 3'6 ur 366 ur 3/6 ur 5hv ur 3)& 6 ur 3'6 ur 366 ur 3/6
samurai-6m/mx adm6996m/mx registers description data sheet 160 rev. 1.31, 2005-11-25 port status 2 p4ds 14 ro port 4 duplex status 0 b , port 4 operates in the half duplex 1 b , port 4 operates in the full duplex p4ss 13 ro port 4 speed status 0 b , port 4 operates in the 10m 1 b , port 4 operates in the 100m p4ls 12 ro port 4 link status 0 b , port 4 links down 1 b , port 4 links up p3fcs 11 ro port 3 flow control status 0 b , port 3 disables the full flow control/half back pressure function 1 b , port 3 enables the full flow control/half back pressure function p3ds 10 ro port 3 duplex status 0 b , port 3 operates in the half duplex 1 b , port 3 operates in the full duplex p3ss 9 ro port 3 speed status 0 b , port 3 operates in the 10m 1 b , port 3 operates in the 100m p3ls 8 ro port 3 link status 0 b , port 3 links down 1 b , port 3 links up. res 7:4 ro reserved p2fcs 3 ro port 2 flow control status 0 b , port 2 disables the full flow control/half back pressure function 1 b , port 2 enables the full flow control/half back pressure function p2ds 2 ro port 2 duplex status 0 b , port 2 operates in the half duplex 1 b , port 2 operates in the full duplex p2ss 1 ro port 2 speed status 0 b , port 2 operates in the 10m 1 b , port 2 operates in the 100m p2ls 0 ro port 2 link status 0 b , port 2 links down 1 b , port 2 links up ps2 offset reset value port status 2 a4 h 0000 h field bits type description ur 5hv ur 3)& ( ur 3'6 ur 5hv ur 366 ur 3/6
data sheet 161 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description port status 3 cable broken 0 field bits type description res 15:5 ro reserved p5fce 4 ro port 5 flow control enable 0 b , port 5 disables the full flow control/half back pressure function 1 b , port 5 enables the full flow control/half back pressure function p5ds 3 ro port 5 duplex status 0 b , port 5 operates in the half duplex 1 b , port 5 operates in the full duplex res 2 ro reserved p5ss 1 ro port 5 speed status 0 b , port 5 operates in the 10m 1 b , port 5 operates in the 100m p5ls 0 ro port 5 link status 0 b , port 5 links down 1 b , port 5 links up ps3 offset reset value port status 3 a5 h 0000 h field bits type description res 15:0 r reserved cb0 offset reset value cable broken 0 a6 h 0000 h field bits type description cb0 15:0 ro reserved u 5hv ur &%
samurai-6m/mx adm6996m/mx registers description data sheet 162 rev. 1.31, 2005-11-25 cable broken 1 counter low 0 similar registers all clx registers have the same structure and characteristics, see cl0 . the offset addresses of the other clx registers are listed in table 63 . cb1 offset reset value cable broken 1 a7 h 0000 h field bits type description cb1 15:0 ro reserved cl0 offset reset value port 0 receive packet counter low a8 h 0000 h field bits type description counter 15:0 rw counter[15:0] table 63 clx registers register short name register long name offset address page number cl1 port 1 receive packet counter low ac h cl2 port 2 receive packet counter low b0 h cl3 port 3 receive packet counter low b4 h cl4 port 4 receive packet counter low b6 h cl5 port 5 receive packet counter low b8 h cl6 port 0 receive packet byte count low ba h cl7 port 1 receive packet byte count low be h cl8 port 2 receive packet byte count low c2 h cl9 port 3 receive packet byte count low c6 h ur &% uz &2817(5
data sheet 163 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description counter high 0 cl10 port 4 receive packet byte count low c8 h cl11 port 5 receive packet byte count low ca h cl12 port 0 transmit packet count low cc h cl13 port 1 transmit packet count low d0 h cl14 port 2 transmit packet count low d4 h cl15 port 3 transmit packet count low d8 h cl16 port 4 transmit packet count low da h cl17 port 5 transmit packet count low dc h cl18 port 0 transmit packet byte count low de h cl19 port 1 transmit packet byte count low e2 h cl20 port 2 transmit packet byte count low e6 h cl21 port 3 transmit packet byte count low ea h cl22 port 4 transmit packet byte count low ec h cl23 port 5 transmit packet byte count low ee h cl24 port 0 collision count low f0 h cl25 port 1 collision count low f4 h cl26 port 2 collision count low f8 h cl27 port 3 collision count low fc h cl28 port 4 collision count low fe h cl29 port 5 collision count low 100 h cl30 port 0 error count low 102 h cl31 port 1 error count low 106 h cl32 port 2 error count low 10a h cl33 port 3 error count low 10e h cl34 port 4 error count low 110 h cl35 port 5 error count low 112 h ch0 offset reset value port 0 receive packet counter high a9 h 0000 h field bits type description counter 15:0 rw counter[31:16] table 63 clx registers (cont?d) register short name register long name offset address page number uz &2817(5
samurai-6m/mx adm6996m/mx registers description data sheet 164 rev. 1.31, 2005-11-25 similar registers all chx registers have the same structure and characteristics, see ch0 . the offset addresses of the other clh registers are listed in table 64 . table 64 chx registers register short name register long name offset address page number ch1 port 1 receive packet counter high ad h ch2 port 2 receive packet counter high b1 h ch3 port 3 receive packet counter high b5 h ch4 port 4 receive packet counter high b7 h ch5 port 5 receive packet counter high b9 h ch6 port 0 receive packet byte count high bb h ch7 port 1 receive packet byte count high bf h ch8 port 2 receive packet byte count high c3 h ch9 port 3 receive packet byte count high c7 h ch10 port 4 receive packet byte count high c9 h ch11 port 5 receive packet byte count high cb h ch12 port 0 transmit packet count high cd h ch13 port 1 transmit packet count high d1 h ch14 port 2 transmit packet count high d5 h ch15 port 3 transmit packet count high d9 h ch16 port 4 transmit packet count high db h ch17 port 5 transmit packet count high dd h ch18 port 0 transmit packet byte count high df h ch19 port 1 transmit packet byte count high e3 h ch20 port 2 transmit packet byte count high e7 h ch21 port 3 transmit packet byte count high eb h ch22 port 4 transmit packet byte count high ed h ch23 port 5 transmit packet byte count high ef h ch24 port 0 collision count high f1 h ch25 port 1 collision count high f5 h ch26 port 2 collision count high f9 h ch27 port 3 collision count high fd h ch28 port 4 collision count high ff h ch29 port 5 collision count high 101 h ch30 port 0 error count high 103 h ch31 port 1 error count high 107 h ch32 port 2 error count high 10b h ch33 port 3 error count high 10f h ch34 port 4 error count high 111 h ch35 port 5 error count high 113 h
data sheet 165 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description over-flow flag 0 off0 offset reset value over-flow flag 0 114 h 0000 h field bits type description p3_bc 15 lhsc overflow of port 3 receive packet byte count 0 b , no overflow 1 b , overflow res 14 ro reserved p2_bc 13 lhsc overflow of port 2 receive packet byte count 0 b , no overflow 1 b , overflow res 12 ro reserved p1_bc 11 lhsc overflow of port 1 receive packet byte count 0 b , no overflow 1 b , overflow res 10 ro reserved p0_bc 9 lhsc overflow of port 0 receive packet byte count 0 b , no overflow 1 b , overflow p5_c 8 lhsc overflow of port 5 receive packet count 0 b , no overflow 1 b , overflow p4_c 7 lhsc overflow of port 4 receive packet count 0 b , no overflow 1 b , overflow p3_c 6 lhsc overflow of port 3 receive packet count 0 b , no overflow 1 b , overflow res 5 ro reserved p2_c 4 lhsc overflow of port 2 receive packet count 0 b , no overflow 1 b , overflow res 3 ro reserved p1_c 2 lhsc overflow of port 1 receive packet count 0 b , no overflow 1 b , overflow res 1 ro reserved okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & okvf 3b& okvf 3b& okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b&
samurai-6m/mx adm6996m/mx registers description data sheet 166 rev. 1.31, 2005-11-25 over-flow flag 1 over-flow flag 2 p0_c 0 lhsc overflow of port 0 receive packet count 0 b , no overflow 1 b , overflow off1 offset reset value over-flow flag 1 115 h 0000 h field bits type description res 15:2 ro reserved p5_bc 1 lhsc overflow of port 5 receive packet byte count 0 b , no overflow 1 b , overflow p4_bc 0 lhsc overflow of port 4 receive packet byte count 0 b , no overflow 1 b , overflow off2 offset reset value over-flow flag 2 116 h 0000 h field bits type description p3_bc 15 lhsc overflow of port 3 transmit packet byte count 0 b , no overflow 1 b , overflow res 14 ro reserved p2_bc 13 lhsc overflow of port 2 transmit packet byte count 0 b , no overflow 1 b , overflow field bits type description ur 5hv okvf 3b% & okvf 3b% & okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & ur 5hv okvf 3b% & okvf 3b& okvf 3b& okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b& ur 5hv okvf 3b&
data sheet 167 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description over-flow flag 3 res 12 ro reserved p1_bc 11 lhsc overflow of port 1 transmit packet byte count 0 b , no overflow 1 b , overflow res 10 ro reserved p0_bc 9 lhsc overflow of port 0 transmit packet byte count 0 b , no overflow 1 b , overflow p5_c 8 lhsc overflow of port 5 transmit packet count 0 b , no overflow 1 b , overflow p4_c 7 lhsc overflow of port 4 transmit packet count 0 b , no overflow 1 b , overflow p3_c 6 lhsc overflow of port 3 transmit packet count 0 b , no overflow 1 b , overflow res 5 ro reserved p2_c 4 lhsc overflow of port 2 transmit packet count 0 b , no overflow 1 b , overflow res 3 ro reserved p1_c 2 lhsc overflow of port 1 transmit packet count 0 b , no overflow 1 b , overflow res 1 ro reserved p0_c 0 lhsc overflow of port 0 transmit packet count 0 b , no overflow 1 b , overflow off3 offset reset value over-flow flag 3 117 h 0000 h field bits type description res 15:2 ro reserved field bits type description ur 5hv okvf 3b% & okvf 3b% &
samurai-6m/mx adm6996m/mx registers description data sheet 168 rev. 1.31, 2005-11-25 over-flow flag 4 p5_bc 1 lhsc overflow of port 5 transmit packet byte count 0 b , no overflow 1 b , overflow p4_bc 0 lhsc overflow of port 4 transmit packet byte count 0 b , no overflow 1 b , overflow off4 offset reset value over-flow flag 4 118 h 0000 h field bits type description p3ec 15 lhsc overflow of port 3 error count 0 b , no overflow 1 b , overflow res 14 ro reserved p2ec 13 lhsc overflow of port 2 error count 0 b , no overflow 1 b , overflow res 12 ro reserved p1ec 11 lhsc overflow of port 1 error count 0 b , no overflow 1 b , overflow res 10 ro reserved p0ec 9 lhsc overflow of port 0 error count 0 b , no overflow 1 b , overflow p5cc 8 lhsc overflow of port 5 collision count 0 b , no overflow 1 b , overflow p4cc 7 lhsc overflow of port 4 collision count 0 b , no overflow 1 b , overflow p3cc 6 lhsc overflow of port 3 collision count 0 b , no overflow 1 b , overflow res 5 ro reserved field bits type description okvf 3(& ur 5hv okvf 3(& ur 5hv okvf 3(& ur 5hv okvf 3(& okvf 3&& okvf 3&& okvf 3&& ur 5hv okvf 3&& ur 5hv okvf 3&& ur 5hv okvf 3&&
data sheet 169 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description over-flow flag 5 hardware setting low register p2cc 4 lhsc overflow of port 2 collision count 0 b , no overflow 1 b , overflow res 3 ro reserved p1cc 2 lhsc overflow of port 1 collision count 0 b , no overflow 1 b , overflow res 1 ro reserved p0cc 0 lhsc overflow of port 0 collision count 0 b , no overflow 1 b , overflow off5 offset reset value over-flow flag 5 119 h 0000 h field bits type description res 15:2 ro reserved p5ec 1 lhsc overflow of port 5 error count 0 b , no overflow 1 b , overflow p4ec 0 lhsc overflow of port 4 error count 0 b , no overflow 1 b , overflow hsl offset reset value hardware setting low register 130 h 0000 h field bits type description ur 5hv okvf 3(& okvf 3(& ur + ur %2 ur '$) ur %3 ur '% ur *0 ur 50 ur 3,7 ur *)& ur 3)0 ur '& ur &$ ur $& ur $1
samurai-6m/mx adm6996m/mx registers description data sheet 170 rev. 1.31, 2005-11-25 hardware setting high register field bits type description h15ro reserved bo 14 ro bond daf 13 ro disable samurai-6m/6mx (adm6996m/mx) function bp 12 ro bpen db 11 ro 16/32 bit data bus gm 10 ro gpsi mode rm 9 ro rmii mode p4it 8:7 ro port 4 interface type gfc 6 ro global flow control p4fm 5 ro port 4 fiber mode dc 4 ro dual color ca 3:2 ro chip address ac 1 ro auto-crossover an 0 ro auto-negotiation hsh offset reset value hardware setting high register 131 h 0000 h field bits type description res 15:10 ro reserved ltbr 9 ro learning table bist result 0 b , works 1 b , doesn?t work lltbr 8 ro linklist table bist result (linklist table does not do bist test in normal mode) 0 b , works 1 b , doesn?t work ctbr 7 ro control table bist result 0 b , works 1 b , doesn?t work hitbr 6 ro hardware igmp table bist result 0 b , works 1 b , doesn?t work ur 5hv ur /7%5 ur //7% 5 ur &7%5 ur +,7% 5 ur '%%5 ur 30 ur 30 ur &)*
data sheet 171 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description assign address [15:0] register assign address [31:16] register dbbr 5 ro data buffer bist result 0 b , works 1 b , doesn?t work p5m 4:3 ro p5 mode 00 b , gpsi 01 b , rmii 10 b , mii p4m 2:1 ro p4 mode 00 b , port 4 uses inner phy 01 b , port 4 uses mii 11 b , port 4 isolated phy cfg 0 ro cfg aa1 offset reset value assign address [15:0] register 132 h 0000 h field bits type description ass_addr 15:0 rw assign address [15:0] aa2 offset reset value assign address [31:16] register 133 h 0000 h field bits type description ass_addr 15:0 rw assign address [31:16] field bits type description uz $66b$''5 uz $66b$''5
samurai-6m/mx adm6996m/mx registers description data sheet 172 rev. 1.31, 2005-11-25 assign address [47:32] register assign option register aa3 offset reset value assign address [47:32] register 134 h 0000 h field bits type description ass_addr 15:0 rw assign address [47:32] ao offset reset value assign option register 135 h 0000 h field bits type description res 15:10 r reserved pac 9 rw pause address change it is useful only when assigned address is used for pause source address 0 b , all the ports use this assigned address as the source address of the pause commands 1 b , port 0 uses {assigned address[47:3], 000 b } as the source address of the pause commands.port 1 uses {assigned address[47:3], 001 b } as the source address of the pause commands.port 2 uses {assigned address[47:3], 010 b } as the source address of the pause commands.port 3 uses {assigned address[47:3], 011 b } as the source address of the pause commands.port 4 uses {assigned address[47:3], 100 b } as the source address of the pause commands.port 5 uses {assigned address[47:3], 101 b } as the source address of the pause commands. uz $66b$''5 u 5hv uz 3$& uz $$2 uz $) uz $3
data sheet 173 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description mirror register 0 aao 8:7 rw assign address option 00 b , assigned address is useless 01 b , assigned address is used for pause source address 10 b , assigned address is used for assigned lock address or the monitor address 11 b , assigned address is used for pause source address af 6:3 rw assign fid it is used for to assign lock fid. ap 2:0 rw assign port it is used for the port that the user wants to assign or for the monitor port. mirr0 offset reset value mirror register 0 136 h 0000 h field bits type description p3tm 15:14 rw port 3 transmit mirror option see register 0136 h , p0tm for more details. p3rm 13:12 rw port 3 receive mirror option see register 0136 h , p0rm for more details. p2tm 11:10 rw port 2 transmit mirror option see register 0136 h , p0tm for more details. p2rm 9:8 rw port 2 receive mirror option see register 0136 h , p0rm for more details. p1tm 7:6 rw port 1 transmit mirror option see register 0136 h , p0tm for more details. p1rm 5:4 rw port 1 receive mirror option see register 0136 h , p0rm for more detail. p0tm 3:2 rw port 0 transmit mirror option 00 b , does not be mirrored 01 b , the traffic transmitted from port 0 is mirrored 10 b , the traffic with da = assign address transmitted from port 0 is mirrored 11 b , the traffic with sa = assign address transmitted from port 0 is mirrored field bits type description uz 370 uz 350 uz 370 uz 350 uz 370 uz 350 uz 370 uz 350
samurai-6m/mx adm6996m/mx registers description data sheet 174 rev. 1.31, 2005-11-25 mirror register 1 p0rm 1:0 rw port 0 receive mirror option 00 b , does not be mirrored 01 b , the traffic received on port 0 is mirrored 10 b , the traffic with da = assign address received on port 0 is mirrored 11 b , the traffic with sa = assign address received on port 0 is mirrored mirr1 offset reset value mirror register 1 137 h 0000 h field bits type description me 15 rw mirror enable 0 b , disable 1 b , enable mca 14 rw mirror crc also 0 b , does not mirror 1 b , mirrors mra 13 rw mirror rxer also 0 b , does not mirror 1 b , mirrors mpa 12 rw mirror pause also 0 b , does not mirror 1 b , mirrors mla 11 rw mirror long also 0 b , does not mirror 1 b , mirrors msa 10 rw mirror short also 0 b , does not mirror 1 b , mirrors res 9 rw reserved etup 8 rw enable transmit unmonitored packet to the mirror port 0 b , mirror port only mirrors the mirrored packets 1 b , mirror port also receives packets that are not mirrored but their output ports also contain the mirror port p5tm 7:6 rw port 5 transmit mirror option see register 0136 h , p0tm for more details. p5rm 5:4 rw port 5 receive mirror option see register 0136 h , p0rm for more details. field bits type description uz 0( uz 0&$ uz 05$ uz 03$ uz 0/$ uz 06$ uz 5hv uz (783 uz 370 uz 350 uz 370 uz 350
data sheet 175 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description security violation port security status 0 p4tm 3:2 rw port 4 transmit mirror option see register 0136 h , p0tm for more details. p4rm 1:0 rw port 4 receive mirror option see register 0136 h , p0rm for more details. svp offset reset value security violation port 138 h 0000 h field bits type description res 15:12 r reserved psi 11:6 rc port source intrusion 0 b , source intrusion did not happen 1 b , source intrusion happened res 5:0 r reserved ss0 offset reset value security status 0 139 h 0000 h field bits type description res 15:12 r reserved fl 11:6 r first lock 0 b , port did not lock the address 1 b , port locked the address pl 5:0 r port locked 0 b , port did not close 1 b , port closed because of source violation field bits type description u 5hv uf 36, u 5hv u 5hv u )/ u 3/
samurai-6m/mx adm6996m/mx registers description data sheet 176 rev. 1.31, 2005-11-25 security status 1 first lock address search ss1 offset reset value security status 1 13a h 0000 h field bits type description res 15:6 r reserved ll 5:0 r link lock 0 b , link lock did not happen 1 b , link lock happened flas offset reset value first lock address search 13b h 0000 h field bits type description res 15:3 r reserved flsp 2:0 rw first lock search port users could write this register to get the lock address and the lock fid (returned in the 13c h , 13d h , 13e h , 13f h ) associated with the port. 000 b , search the address and fid locked on the port 0 001 b , search the address and fid locked on the port 1 010 b , search the address and fid locked on the port 1 011 b , search the address and fid locked on the port 1 100 b , search the address and fid locked on the port 1 101 b , search the address and fid locked on the port 1 u 5hv u // u 5hv uz )/63
data sheet 177 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description first lock address [15:0] first lock address [31:16] first lock address [47:32] fla1 offset reset value first lock address [15:0] 13c h 0000 h field bits type description fla 15:0 r first lock address [15:0] fla2 offset reset value first lock address [31:16] 13d h 0000 h field bits type description fla 15:0 r first lock address [31:16] fla3 offset reset value first lock address [47:32] 13e h 0000 h field bits type description fla 15:0 r first lock address [47:32] u )/$ u )/$ u )/$
samurai-6m/mx adm6996m/mx registers description data sheet 178 rev. 1.31, 2005-11-25 first lock fid counter control low register flf offset reset value first lock fid 13f h 0000 h field bits type description res 15:4 r reserved flf 3:0 r first lock fid ccl offset reset value counter control low register 140 h 0000 h field bits type description res 15:8 r reserved bas 7 rw busy/access start 0 b , the counter control is free 1 b , the counter control is busy, or users should write 1 b into this bit to start the access when the engine is free c6rw counter 0 b , indirect read counter 1 b , renew port counter irc_rpc 5:0 rw indirect read counter it means the counter address renew port counter it means the counters on each port to renew u 5hv u )/) u 5hv uz %$6 uz & uz ,5&b53&
data sheet 179 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description counter control high register counter status low register counter status high register cch offset reset value counter control high register 141 h 0000 h field bits type description res 15:0 r reserved csl offset reset value counter status low register 142 h 0000 h field bits type description counter 15:0 r counter [15:0] csh offset reset value counter status high register 143 h 0000 h field bits type description counter 15:0 r counter [31:16] u 5hv u &2817(5 u &2817(5
samurai-6m/mx adm6996m/mx registers description data sheet 180 rev. 1.31, 2005-11-25 4.4 phy registers phy control register of port 0 phy_c0 offset reset value phy control register of port 0 200 h 3100 h field bits type description rst 15 rw, sc reset setting this bit initiates the software reset function that resets the selected port, except for the phase-locked loop circuit. it will re-latch in all hardware configuration pin values the software reset process takes 25 ? s to complete. this bit, which is self-clearing, returns a value of 1 until the reset process is complete. 0 b , normal operation 1 b , phy reset lpbk 14 rw loop back enable this bit controls the phy loopback operation that isolates the network transmitter outputs (txp and txn) and routes the mii transmit data to the mii receive data path. this function should only be used when auto negotiation is disabled (bit 12 = 0). the specific phy (10base-t or 100base-x) used for this operation is determined by bits 12 and 13 of this register 0 b , disable loopback mode 1 b , enable loopback mode speed_lsb 13 rw speed selection lsb, 0.6, 0.13 link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored).if it is fiber mode, 0.13 is always 1. any write to this bit will have no effect. 00 b , 10 mbit/s 01 b , 100 mbit/s 10 b , 1000 mbit/s 11 b , reserved anen 12 rw auto negotiation enable this bit determines whether the link speed should set up by the auto negotiation process or not. it is set at power up or reset if the recanen pin detects a logic 1 input level in twisted-pair mode.if it is set when fiber mode is configured, any write to this bit will be ignored . 0 b , disable auto negotiation process 1 b , enable auto negotiation process uzvf 567 uz /3%. uz 63(( 'b/ uz $1(1 uz 3'1 uz ,62 uzvf $1(1 b567 uz '3/; uz &2/7 67 ur 63(( 'b0 5hv
data sheet 181 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers all phy_cx registers have the same structure and characteristics, see phy_c0 . the offset addresses of the other phy_cx registers are listed in table 65 . pdn 11 rw power down enable setting this bit high puts the phy into power down mode. during the power down mode, txp/txn and all led outputs are tristated and the mii interfaces are isolated. 0 b , normal operation 1 b , power down iso 10 rw isolate phy from network setting this control bit isolates the part from the mii, with the exception of the serial management interface. when this bit is asserted, the phy does not respond to txd, txen and txer inputs, and it presents a high impedence on its txc, rxc, crsdv, rxer, rxd , col and crs outputs. 0 b , normal operation 1 b , isolate phy from mii anen_rst 9 rw, sc restart auto negotiation setting this bit while auto negotiation is enabled it forces a new auto negotiation process to start. this bit is self-clearing and returns to 0 after the auto negotiation process has commenced. 0 b , normal operation 1 b , restart auto negotiation process dplx 8 rw duplex mode if auto negotiation is disabled, this bit determines the duplex mode for the link. 0 b , half duplex mode 1 b , full duplex mode coltst 7 rw collision test when set, this bit will cause the col signal of mii interface to be asserted in response to the assertion of txen. 0 b , disable col signal test 1 b , enable col signal test speed_msb 6 ro speed selection msb set to 0 all the time to indicate that the phy does not support 1000 mbit/s function. table 65 phy_cx registers register short name register long name offset address page number phy_c1 phy control register of port 1 220 h phy_c2 phy control register of port 2 240 h phy_c3 phy control register of port 3 260 h phy_c4 phy control register of port 4 280 h field bits type description
samurai-6m/mx adm6996m/mx registers description data sheet 182 rev. 1.31, 2005-11-25 phy status register of port 0 phy_s0 offset reset value phy status register of port 0 201 h 7849 h field bits type description cap_t4 15 ro 100base-t4 capable set to 0 all the time to indicate that the phy does not support 100base-t4 cap_txf 14 ro 100base-x full duplex capable set to 1 all the time to indicate that the phy does support full duplex mode cap_txh 13 ro 100base-x half duplex capable set to 1 all the time to indicate that the phy does support half duplex mode cap_tf 12 ro 10m full duplex capable tp : set to 1 all the time to indicate that the phy does support 10m full duplex mode fx : set to 0 all the time to indicate that the phy does not support 10m full duplex mode cap_th 11 ro 10m half duplex capable tp : set to 1 all the time to indicate that the phy does support 10m half duplex mode fx : set to 0 all the time to indicate that the phy does not support 10m half duplex mode cap_t2 10 ro 100base-t2 capable set to 0 all the time to indicate that the phy does not support 100base-t2 cap_supr 6 ro mf preamble suppression capable this bit is hardwired to 1 indicating that the phy accepts management frame without preamble. minimum 32 preamble bits are required following power-on or hardware reset. one idle bit is required between any two management transactions as per ieee 802.3u specification. an_comp 5 ro auto negotiation complete if auto negotiation is enabled, this bit indicates whether the auto negotiation process has been completed or not. set to 0 all the time when fiber mode is selected. 0 b , auto negotiation process not completed 1 b , auto negotiation process completed ur &$3b 7 ur &$3b 7;) ur &$3b 7;+ ur &$3b 7) ur &$3b 7+ ur &$3b 7 5hv ur &$3b 6835 ur $1b& 203 ur 5(0b )/7 ur &$3b $1(* ur /,1. ur -$% ur (;75 (*
data sheet 183 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers all phy_sx registers have the same structure and characteristics, see phy_s0 . the offset addresses of the other phy_sx registers are listed in table 66 . phy identifier register of port 0 (a) rem_flt 4 ro remote fault detect this bit is latched to 1 if the rf bit in the auto negotiation link partner ability register (bit 13, register address 05 h ) is set or the receive channel meets the far end fault indication function criteria. it is unlatched when this register is read. 0 b , remote fault not detected 1 b , remote fault detected cap_aneg 3 ro auto negotiation ability tp : this bit is set to 1 all the time, indicating that phy is capable of auto negotiation. fx : this bit is set to 0 all the time, indicating that phy is not capable of auto negotiation in fiber mode. 0 b , not capable of auto negotiation 1 b , capable of auto negotiation link 2 ro link status this bit reflects the current state of the link ? test-fail state machine. loss of a valid link causes a 0 latched into this bit. it remains 0 until this register is read by the serial management interface. whenever linkup, this bit should be read twice to get link up status 0 b , link is down 1 b , link is up jab 1 ro jabber detect 0 b , jabber condition not detected 1 b , jabber condition detected extreg 0 ro extended capability this bit defaults to 1, indicating that the phy implements extended registers. 0 b , no extended register set 1 b , extended register set table 66 phy_sx registers register short name register long name offset address page number phy_s1 phy status register of port 1 221 h phy_s2 phy status register of port 2 241 h phy_s3 phy status register of port 3 261 h phy_s4 phy status register of port 4 281 h phy_i0_a offset reset value phy identifier register of port 0 (a) 202 h 0302 h field bits type description
samurai-6m/mx adm6996m/mx registers description data sheet 184 rev. 1.31, 2005-11-25 similar registers all phy_ix_a registers have the same structure and characteristics, see phy_i0_a . the offset addresses of the other phy_ix_a registers are listed in table 67 . phy identifier register of port 0 (b) similar registers all phy_ix_b registers have the same structure and characteristics, see phy_i0_b . the offset addresses of the other phy_ix_b registers are listed in table 68 . field bits type description phy_id 15:0 ro ieee address table 67 phy_ix_a registers register short name register long name offset address page number phy_i1_a phy identifier register of port 1 (a) 222 h phy_i2_a phy identifier register of port 2 (a) 242 h phy_i3_a phy identifier register of port 3 (a) 262 h phy_i4_a phy identifier register of port 4 (a) 282 h phy_i0_b offset reset value phy identifier register of port 0 (b) 203 h 6071 h field bits type description phy_id 15:10 ro ieee address model_id 9:4 ro ieee model no. rev_id 3:0 ro ieee revision no. table 68 phy_ix_b registers register short name register long name offset address page number phy_i1_b phy identifier register of port 1 (b) 223 h phy_i2_b phy identifier register of port 2 (b) 243 h ur 3+<b,' ur 3+<b,' ur 0rghob,' ur 5(9b,'
data sheet 185 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description auto negotiation advertisement register of port 0 phy_i3_b phy identifier register of port 3 (b) 263 h phy_i4_b phy identifier register of port 4 (b) 283 h anap0 offset reset value auto negotiation advertisement register of port 0 204 h 05e1 h field bits type description np 15 ro next page this bit defaults to 1, indicating that phy is next page capable rf 13 ro remote fault this bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. 0 b , no remote fault has been detected 1 b , remote fault has been detected asm_dir 11 rw asymmetric pause direction bit[ 11:10 ] capability 00 b , no pause 01 b , symmetric pause 10 b , asymmetric pause toward link partner 11 b , both symmetric pause and asymmetric pause toward local device pause 10 rw pause operation for full duplex value on paurec will be stored in this bit during power on reset. t4 9 ro technology ability for 100base-t4 defaults to 0. tx_fdx 8 rw 100base-tx full duplex 0 b , not capable of 100m full duplex operation 1 b , capable of 100m full duplex operation tx_hdx 7 rw 100base-tx half duplex 0 b , not capable of 100m operation 1 b , capable of 100m operation 10_fdx 6 rw 10base-t full duplex 0 b , not capable of 10m full duplex operation 1 b , capable of 10m full duplex operation table 68 phy_ix_b registers (cont?d) register short name register long name offset address page number ur 13 5hv ur 5) 5hv uz $60b ',5 uz 3$86 ( ur 7 uz 7;b) '; uz 7;b+ '; uz b) '; uz b+ '; ur 6)
samurai-6m/mx adm6996m/mx registers description data sheet 186 rev. 1.31, 2005-11-25 similar registers all anapx registers have the same structure and characteristics, see anap0 . the offset addresses of the other anapx registers are listed in table 69 . auto negotiation link partner ability register of port 0 10_hdx 5 rw 10base-t half duplex note: bit 8:5 should be combined with rec100, recful pin input to determine the finalized speed and duplex mode. 0 b , not capable of 10m operation 1 b , capable of 10m operation sf 4:0 ro selector field these 5 bits are hardwired to 00001 b , indicating that the phy supports ieee 802.3 csma/cd. table 69 anapx registers register short name register long name offset address page number anap1 auto negotiation advertisement register of port 1 224 h anap2 auto negotiation advertisement register of port 2 244 h anap3 auto negotiation advertisement register of port 3 264 h anap4 auto negotiation advertisement register of port 4 284 h anlpa0 offset reset value auto negotiation link partner ability register of port 0 205 h 01e1 h field bits type description npage 15 ro next page 0 b , not capable of next page function 1 b , capable of next page function ack 14 ro acknowledge 0 b , not acknowledged 1 b , link partner acknowledges reception of the ability data word rf 13 ro remote fault 0 b , no remote fault has been detected 1 b , remote fault has been detected lp_dir 11 ro link partner asymmetric pause direction field bits type description ur 13$* ( ur $&. ur 5) 5hv ur /3b' ,5 ur /3b3 $8 ur /3b7 ur /3b) '; ur /3b+ '; ur /3b) ur /3b+ ur 6)
data sheet 187 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers all anlpax registers have the same structure and characteristics, see anlpa0 . the offset addresses of the other anlpax registers are listed in table 70 . auto negotiation expansion register of port 0 lp_pau 10 ro link partner pause capabilityvalue on paurec will be stored in this bit during power on reset. lp_t4 9 ro link partner technology ability for 100base-t4defaults to 0. lp_fdx 8 ro 100base-tx full duplex 0 b , not capable of 100m full duplex operation 1 b , capable of 100m full duplex operation lp_hdx 7 ro 100base-tx half duplex 0 b , not capable of 100m operation 1 b , capable of 100m operation lp_f10 6 ro 10base-t full duplex 0 b , not capable of 10m full duplex operation 1 b , capable of 10m full duplex operation lp_h10 5 ro 10base-t half duplex 0 b , not capable of 10m operation 1 b , capable of 10m operation sf 4:0 ro selector field encoding definitions table 70 anlpax registers register short name register long name offset address page number anlpa1 auto negotiation link partner ability register of port 1 225 h anlpa2 auto negotiation link partner ability register of port 2 245 h anlpa3 auto negotiation link partner ability register of port 3 265 h anlpa4 auto negotiation link partner ability register of port 4 285 h ane0 offset reset value auto negotiation expansion register of port 0 206 h 0000 h field bits type description 5hv urok 3)$8 /7 ur /313 $%/( ur 13$% /( ur 3*5& 9 ur /3$1 $%/(
samurai-6m/mx adm6996m/mx registers description data sheet 188 rev. 1.31, 2005-11-25 similar registers all anex registers have the same structure and characteristics, see ane0 . the offset addresses of the other anex registers are listed in table 71 . next page transmit register of port 0 field bits type description pfault 4 ro, lh parallel detection fault 0 b , no fault has been detected 1 b , fault has been detected lpnpable 3 ro link partner next page able 0 b , link partner is not next page capable 1 b , link partner is next page capable npable 2 ro next page able defaults to 0, indicating phy is not capable of next page. pgrcv 1 ro page received 0 b , no new page has been received 1 b , a new page has been received lpanable 0 ro link partner auto negotiation able 0 b , link partner is not auto negotiable 1 b , link partner is auto negotiable table 71 anex registers register short name register long name offset address page number ane1 auto negotiation expansion register of port 1 226 h ane2 auto negotiation expansion register of port 2 246 h ane3 auto negotiation expansion register of port 3 266 h ane4 auto negotiation expansion register of port 4 286 h npt0 offset reset value next page transmit register of port 0 207 h 2001 h field bits type description tnpage 15 ro transmit next page transmit code word bit 15 tmsg 13 rw transmit message page transmit code word bit 13 ur 713$ *( 5hv uz 706* uz 7$&. ur 772* uz 7)/'
data sheet 189 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx registers description similar registers all nptx registers have the same structure and characteristics, see npt0 . the offset addresses of the other nptx registers are listed in table 72 . link partner next page register of port 0 tack2 12 rw transmit acknowledge 2 transmit code word bit 12 ttog 11 ro transmit toggle transmit code word bit 11 tfld 10:0 rw transmit message field transmit code word bit 10..0 table 72 nptx registers register short name register long name offset address page number npt1 next page transmit register of port 1 227 h npt2 next page transmit register of port 2 247 h npt3 next page transmit register of port 3 267 h npt4 next page transmit register of port 4 287 h lpnp0 offset reset value link partner next page register of port 0 208 h 0000 h field bits type description pnpage 15 ro link partner next page receives code word bit 15 pack 14 ro link partner acknowledge receives code word bit 14 pmsgp 13 ro link partner message page receives code word bit 13 pack2 12 ro link partner acknowledge 2 receives code word bit 12 ptog 11 ro link partner toggle receives code word bit 11 pfld 10:0 ro link partner message field receives code word bit 11 field bits type description ur 313$ *( ur 3$&. ur 306* 3 ur 3$&. ur 372* ur 3)/'
samurai-6m/mx adm6996m/mx registers description data sheet 190 rev. 1.31, 2005-11-25 similar registers all lpnpx registers have the same structure and characteristics, see lpnp0 . the offset addresses of the other lpnpx registers are listed in table 73 . table 73 lpnpx registers register short name register long name offset address page number lpnp1 link partner next page register of port 1 228 h lpnp2 link partner next page register of port 2 248 h lpnp3 link partner next page register of port 3 268 h lpnp4 link partner next page register of port 4 288 h
data sheet 191 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5 electrical specification 5.1 tx/fx interface 5.1.1 tp interface figure 18 tp interface transformer requirements: ?tx/rx rate 1:1 ? tx/rx central tap connect together to vcca2 users can change the tx/rx pin for easy layout but do not change the polarity. samurai-6m/6mx (adm6996m/mx) supports auto polarity on the receiving side. txp txn adm6996 rxp rxn 49.9 49.9 49.9 49.9 0.01u 0.01u 1:1 1:1 auto-mdix x'fmr 1 2 3 4 5 6 7 8 rj-45 vcca2 75 75 75 0.1u hi-pot cap r1 r2 c1
samurai-6m/mx adm6996m/mx electrical specification data sheet 192 rev. 1.31, 2005-11-25 5.1.2 fx interface figure 19 fx interface 5.2 dc characterization table 74 power consumption parameter symbol values unit note / test condition min. typ. max. power consumption when all twisted pair ports are linked at 100 mbit/s. p 100m_5tp ?980?mwunder eeprom register 29 h = c000 h , and 30 h = 985 h power consumption when all twisted pair ports are linked at 10 mbit/s (include transformer). p 10m_5tp ? 1450 ? mw under eeprom register 29 h = c000 h , and 30 h = 985 h power consumption when all twisted pair ports are disconnected. p dis_5tp ?500?mwunder eeprom register 29 h = c000 h , and 30 h = 985 h txp txn adm6996 rxp rxn 69 1 gnd_rx 2 rd+ 3 rd- 4 sd 5 vcc_rx 6 vcc_tx 7 td- 8 td+ 9 gnd_tx 3.3v fiber transceiver 69 182 182 127 127 83 83 +3.3v +3.3v 83 127 +3.3v sd sd vcc(3.3) vcc(3.3)
data sheet 193 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 75 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. 3.3 v power supply for i/o pad v cc3o 2.97 3.3 3.63 v ? 3.3 v power supply for bias circuit v ccbs 2.97 3.3 3.63 v ? 3.3 v power supply for a/d converter v ccad 2.97 3.3 3.63 v ? 1.8 v power supply for line driver v cca2 1.62 1.8 1.98 v ? 1.8 v power supply for pll v ccpll 1.62 1.8 1.98 v ? 1.8 v power supply for digital core v ccik 1.62 1.8 1.98 v ? input voltage v in -0.3 ? v cc3o + 0.3 v? output voltage v out -0.3 ? v cc3o + 0.3 v? maximum current for 3.3 v power supply i 3.3vmax ? ? 100 ma ? maximum current for 1.8 v power supply (include transformer) i 1.8vmax ? ? 800 ma ? storage temperature t stg -55 ? 155 c ? esd rating esd 1.0 ? ? kv ? table 76 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. 3.3 v power supply for i/o pad v cc3o 3.135 3.3 3.465 v ? 3.3 v power supply for bias circuit v ccbs 3.135 3.3 3.465 v ? 3.3 v power supply for a/d converter v ccad 3.135 3.3 3.465 v ? 1.8 v power supply for line driver v cca2 1.71 1.8 1.89 v ? 1.8 v power supply for pll v ccpll 1.71 1.8 1.89 v ? 1.8 v power supply for digital core v ccik 1.71 1.8 1.89 v ? input voltage v in 0? v cc v? junction operating temperature t j 0 25 115 c ?
samurai-6m/mx adm6996m/mx electrical specification data sheet 194 rev. 1.31, 2005-11-25 5.3 ac characterization 5.3.1 xtal/osc timing figure 20 xtal/osc timing table 77 dc electrical characteristics for 3.3 v operation 1) 1) under v cc3o = 2.97v ~ 3.63 v, t j = 0 c ~ 115 c parameter symbol values unit note / test condition min. typ. max. input low voltage v il ??0.8vttl input high voltage v ih 2.0 ? ? v ttl output low voltage v ol ??0.4vttl output high voltage v oh 2.4 ? ? v ttl input pull-up/down resistance r i ?50?k ? v il = 0 v or v ih = v cc3o table 78 xtal/osc timing parameter symbol values unit note / test condition min. typ. max. xi/osci clock period t _xi_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? xi/osci clock high t _xi_hi 14 20.0 ? ns ? xi/osci clock low t _xi_lo 14 20.0 ? ns ? xi/osci clock rise time, v il (max) to v ih (min.) t _xi_rise ??4ns? xi/osci clock fall time, v ih (min.) to v il (max) t _xi_fall ??4ns? t xi_rise t xi_fall t xi_hi t xi_lo t xi_per v il-xi v ih-xi
data sheet 195 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5.3.2 power on reset figure 21 power on reset timing 5.3.3 eeprom interface timing figure 22 eeprom interface timing table 79 power on reset timing parameter symbol values unit note / test condition min. typ. max. rst low period t rst 100 ? ? ms ? start of idle pulse width t conf 100 ? ? ns ? table 80 eeprom interface timing parameter symbol values unit note / test condition min. typ. max. eesk period t esk ? 5120 ? ns ? eesk low period t eskl 2550 ? 2570 ns ? eesk high period t eskh 2550 ? 2570 ns ? tconf trst trst 0us 50us 100us 150us rst* all configuration pins terdh terds tewdd tesk tesk teskl teskl teskh teskh 0us 10us 20us 30us eecs eesk eedo eedi
samurai-6m/mx adm6996m/mx electrical specification data sheet 196 rev. 1.31, 2005-11-25 5.3.4 10base-tx mii input timing figure 23 10base-tx mii input timing eedi to eesk rising setup time t erds 10 ? ? ns ? eedi to eesk rising hold time t erdh 10 ? ? ns ? eesk falling to eedo output delay time t ewdd ??20ns? table 81 10base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck ?400?ns? mii_rxclk low period t ckl 180 ? 220 ns ? mii_rxclk high period t ckh 180 ? 220 ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising setup t rxs 10 ? ? ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising hold t rxh 10 ? ? ns ? table 80 eeprom interface timing (cont?d) parameter symbol values unit note / test condition min. typ. max. 0ns 2000ns 1000ns tck tck mii_rxclk tckh tckh tckl tckl trxs trxh mii_rxdv mii_rxd mii_crs
data sheet 197 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5.3.5 10base-tx mii output timing figure 24 10base-tx mii output timing table 82 10-base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck ?400?ns? mii_txclk low period t ckl 180 ? 220 ns ? mii_txclk high period t ckh 180 ? 220 ns ? mii_txd, mii_txen to mii_txclk rising output delay t txod 0?25ns? 0ns 500ns 1000ns 2000ns 1500ns 2500ns mii_txen mii_txd mii_txclk tckh tckh tckl tckl tck tck ttxod
samurai-6m/mx adm6996m/mx electrical specification data sheet 198 rev. 1.31, 2005-11-25 5.3.6 100base-tx mii input timing figure 25 100base-tx mii input timing table 83 100base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck ?40?ns? mii_rxclk low period t ckl 18 ? 22 ns ? mii_rxclk high period t ckh 18 ? 22 ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising setup t rxs 10 ? ? ns ? mii_crs, mii_rxdv and mii_rxd to mii_rxclk rising hold t rxh 10 ? ? ns ? 0ns 100ns 200ns tck tck mii_rxclk tckh tckh tckl tckl trxs trxh mii_rxdv mii_rxd mii_crs
data sheet 199 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5.3.7 100base-tx mii output timing figure 26 100base-tx mii output timing 5.3.8 rmii refclk input timing figure 27 rmii refclk input timing table 84 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck ?40?ns? mii_txclk low period t ckl 18 ? 22 ns ? mii_txclk high period t ckh 18 ? 22 ns ? mii_txd, mii_txen to mii_txclk rising output delay t txod 0?25ns? 0ns 50ns 100ns 200ns 150ns 250ns mii_txen mii_txd mii_txclk tckh tckh tckl tckl tck tck ttxod t in50_rise t in50_fall t in50_hi t in50_lo t in50_per v il-rmii v ih-rmii
samurai-6m/mx adm6996m/mx electrical specification data sheet 200 rev. 1.31, 2005-11-25 5.3.9 rmii refclk output timing figure 28 rmii refclk output timing table 85 rmii refclk input timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t in50_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? refclk clock high t in50_hi 14 20.0 ? ns ? refclk clock low t in50_lo 14 20.0 ? ns ? refclk clock rise time, v il (max) to v ih (min.) t in50_rise ??2ns? refclk clock fall time, v ih (min.) to v il (max) t in50_fall ??2ns? table 86 rmii refclk output timing parameter symbol values unit note / test condition min. typ. max. refclk clock period t out50_per 40.0 - 50ppm 40.0 40.0 + 50ppm ns ? refclk clock high t out50_hi 14 20.0 26 ns ? refclk clock low t out50_lo 14 20.0 26 ns ? refclk clock rise time, v ol (max) to v oh (min.) t out50_rise ??2ns? refclk clock fall time, v oh (min.) to v ol (max) t out50_fall ??2ns? refclk clock jittering (p-p) t out50_jit ?0.15?ns? t out50_rise t out50_fall t out50_hi t out50_lo t out50_per v ol-rmii v oh-rmii
data sheet 201 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5.3.10 reduce mii timing figure 29 reduce mii timing (1 of 2) figure 30 reduce mii timing (2 of 2) table 87 reduce mii timing parameter symbol values unit note / test condition min. typ. max. rmii_refclk period t ck ?20?ns? rmii_refclk low period t ckl ?10?ns? rmii_refclk high period t ckh ?10?ns? txen, txd to refclk rising setup time t txs 4??ns? txe, txd to refclk rising hold time t txh 2??ns? csrdv, rxd to refclk rising setup time t rxs 4?? ? crsdv, rxd to refclk rising hold time t rxh 2?? ? ttxh ttxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_txen txd[1:0] trxh trxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_crsdv rxd[1:0]
samurai-6m/mx adm6996m/mx electrical specification data sheet 202 rev. 1.31, 2005-11-25 5.3.11 gpsi (7-wire) input timing figure 31 gpsi (7-wire) input timing table 88 gpsi (7-wire) input timing parameter symbol values unit note / test condition min. typ. max. gpsi_rxclk period t ck ?100?ns? gpsi_rxclk low period t ckl 40 ? 60 ns ? gpsi_rxclk high period t ckh 40 ? 60 ns ? gpsi_rxd, gpsi_crs/col to gpsi_rxclk rising setup time t rxs 10 ? ? ns ? gpsi_rxd, gpsi_crs/col to gpsi_rxclk rising holdtime t rxh 10 ? ? ns ? 0ns 500ns 250ns gpsi_crs/col gpsi_rxd gpsi_rxclk tckh tckh tckl tckl tck tck trxh trxs
data sheet 203 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx electrical specification 5.3.12 gpsi (7-wire) output timing figure 32 gpsi (7-wire) output timing 5.3.13 sdc/sdio timing figure 33 sdc/sdio timing table 89 gpsi (7-wire) output timing parameter symbol values unit note / test condition min. typ. max. gpsi_txclk period t ck ?100?ns? gpsi_txclk low period t ckl 40 ? 60 ns ? gpsi_txclk high period t ckh 40 ? 60 ns ? gpsi_txclk rising to gpsi_txen/gpsi_txd output delay t od 50 ? 70 ns ? 0ns 500ns 250ns tckh tckh tckl tckl tck tck tod gpsi_txclk gpsi_txd gpsi_txen tsdh tsds tsdc tsdcl tsdcl tsdch tsdc tsdch 0ns 25ns 50ns 75ns 100 ns sdc sdio
samurai-6m/mx adm6996m/mx electrical specification data sheet 204 rev. 1.31, 2005-11-25 5.3.14 mdc/mdio timing figure 34 mdc/mdio timing table 90 sdc/sdio timing parameter symbol values unit note / test condition min. typ. max. sdc period t ck 20 ? ? ns ? sdc low period t ckl 10 ? ? ns ? sdc high period t ckh 10 ? ? ns ? sdio to sdc rising setup time on read/write cycle t sds 4??ns? sdio to sdc rising hold time on read/write cycle t sdh 2??ns? table 91 mdc/mdio timing parameter symbol values unit note / test condition min. typ. max. mdc period t mdc 100 ? ? ns ? mdc low period t mdcl 40 ? ? ns ? mdc high period t mdch 40 ? ? ns ? mdio to mdc rising setup time on read/write cycle t mds ??10ns? mdio to mdc rising hold time on read/write cycle t mdh 10 ? ? ns ? tmdh tmds tmdcl tmdc tmdch 0ns 25ns 50ns 75ns 100ns mdc mdio
data sheet 205 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx package outlines 6 package outlines figure 35 p-pqfp-128 outside dimension 6.1 package information product name product type package 6-port 10/100 mbit/s single chip ethernet switch controller samurai-6m/mx, adm6996m/mx- ac-t-1, version ac p-pqfp-128
samurai-6m/mx adm6996m/mx terminology data sheet 206 rev. 1.31, 2005-11-25 terminology b ber bit error rate c cfi canonical format indicator col collision crc cyclic redundancy check crs carrier sense cs chip select d da destination address di data input do data output e edi eeprom data input edo eeprom data output eecs eeprom chip select eesk eeprom clock esd end of stream delimiter f fefi far end fault indication fet field effect transistor flp fast link pulse g gnd ground gpsi general purpose serial interface i ipg inter-packet gap l lfsr linear feedback shift register m mac media access controller mdix mdi crossover mii media independent interface n nrzi non return to zero inverter nrz non return to zero p pcs physical coding sub-layer phy physical layer pll phase lock loop pma physical medium attachment
data sheet 207 rev. 1.31, 2005-11-25 samurai-6m/mx adm6996m/mx terminology pmd physical medium dependent q qos quality of service qfp quad flat package r rst reset rxclk receive clock rxd receive data rxdv receive data valid rxer receive data errors rxn receive negative (analog receive differential signal) rxp receive positive (analog receive differential signal) s sa source address soho small office home office ssd start of stream delimiter sqe signal quality error t tos type of service tp twisted pair ttl transistor logic txclk transmission clock txd transmission data txen transmission enable txn transmission negative txp transmission positive
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